1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Marvell
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define pr_fmt(fmt) "mvebu-cpureset: " fmt
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/resource.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "common.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static void __iomem *cpu_reset_base;
22*4882a593Smuzhiyun static size_t cpu_reset_size;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define CPU_RESET_OFFSET(cpu) (cpu * 0x8)
25*4882a593Smuzhiyun #define CPU_RESET_ASSERT BIT(0)
26*4882a593Smuzhiyun
mvebu_cpu_reset_deassert(int cpu)27*4882a593Smuzhiyun int mvebu_cpu_reset_deassert(int cpu)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun u32 reg;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (!cpu_reset_base)
32*4882a593Smuzhiyun return -ENODEV;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (CPU_RESET_OFFSET(cpu) >= cpu_reset_size)
35*4882a593Smuzhiyun return -EINVAL;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun reg = readl(cpu_reset_base + CPU_RESET_OFFSET(cpu));
38*4882a593Smuzhiyun reg &= ~CPU_RESET_ASSERT;
39*4882a593Smuzhiyun writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu));
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
mvebu_cpu_reset_map(struct device_node * np,int res_idx)44*4882a593Smuzhiyun static int mvebu_cpu_reset_map(struct device_node *np, int res_idx)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct resource res;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (of_address_to_resource(np, res_idx, &res)) {
49*4882a593Smuzhiyun pr_err("unable to get resource\n");
50*4882a593Smuzhiyun return -ENOENT;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (!request_mem_region(res.start, resource_size(&res),
54*4882a593Smuzhiyun np->full_name)) {
55*4882a593Smuzhiyun pr_err("unable to request region\n");
56*4882a593Smuzhiyun return -EBUSY;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun cpu_reset_base = ioremap(res.start, resource_size(&res));
60*4882a593Smuzhiyun if (!cpu_reset_base) {
61*4882a593Smuzhiyun pr_err("unable to map registers\n");
62*4882a593Smuzhiyun release_mem_region(res.start, resource_size(&res));
63*4882a593Smuzhiyun return -ENOMEM;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun cpu_reset_size = resource_size(&res);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
mvebu_cpu_reset_init(void)71*4882a593Smuzhiyun static int __init mvebu_cpu_reset_init(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct device_node *np;
74*4882a593Smuzhiyun int res_idx;
75*4882a593Smuzhiyun int ret;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL,
78*4882a593Smuzhiyun "marvell,armada-370-cpu-reset");
79*4882a593Smuzhiyun if (np) {
80*4882a593Smuzhiyun res_idx = 0;
81*4882a593Smuzhiyun } else {
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * This code is kept for backward compatibility with
84*4882a593Smuzhiyun * old Device Trees.
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL,
87*4882a593Smuzhiyun "marvell,armada-370-xp-pmsu");
88*4882a593Smuzhiyun if (np) {
89*4882a593Smuzhiyun pr_warn(FW_WARN "deprecated pmsu binding\n");
90*4882a593Smuzhiyun res_idx = 1;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* No reset node found */
95*4882a593Smuzhiyun if (!np)
96*4882a593Smuzhiyun return -ENODEV;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ret = mvebu_cpu_reset_map(np, res_idx);
99*4882a593Smuzhiyun of_node_put(np);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return ret;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun early_initcall(mvebu_cpu_reset_init);
105