1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-mv78x00/rd78x00-masa-setup.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Marvell RD-78x00-mASA Development Board Setup
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/ata_platform.h>
15*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
16*4882a593Smuzhiyun #include <linux/ethtool.h>
17*4882a593Smuzhiyun #include <asm/mach-types.h>
18*4882a593Smuzhiyun #include <asm/mach/arch.h>
19*4882a593Smuzhiyun #include "mv78xx0.h"
20*4882a593Smuzhiyun #include "common.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = {
23*4882a593Smuzhiyun .phy_addr = MV643XX_ETH_PHY_ADDR(8),
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = {
27*4882a593Smuzhiyun .phy_addr = MV643XX_ETH_PHY_ADDR(9),
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = {
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = {
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static struct mv_sata_platform_data rd78x00_masa_sata_data = {
37*4882a593Smuzhiyun .n_ports = 2,
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
rd78x00_masa_init(void)40*4882a593Smuzhiyun static void __init rd78x00_masa_init(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * Basic MV78x00 setup. Needs to be called early.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun mv78xx0_init();
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * Partition on-chip peripherals between the two CPU cores.
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun if (mv78xx0_core_index() == 0) {
51*4882a593Smuzhiyun mv78xx0_ehci0_init();
52*4882a593Smuzhiyun mv78xx0_ehci1_init();
53*4882a593Smuzhiyun mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
54*4882a593Smuzhiyun mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
55*4882a593Smuzhiyun mv78xx0_sata_init(&rd78x00_masa_sata_data);
56*4882a593Smuzhiyun mv78xx0_uart0_init();
57*4882a593Smuzhiyun mv78xx0_uart2_init();
58*4882a593Smuzhiyun } else {
59*4882a593Smuzhiyun mv78xx0_ehci2_init();
60*4882a593Smuzhiyun mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
61*4882a593Smuzhiyun mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
62*4882a593Smuzhiyun mv78xx0_uart1_init();
63*4882a593Smuzhiyun mv78xx0_uart3_init();
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
rd78x00_pci_init(void)67*4882a593Smuzhiyun static int __init rd78x00_pci_init(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * Assign all PCIe devices to CPU core #0.
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0)
73*4882a593Smuzhiyun mv78xx0_pcie_init(1, 1);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun subsys_initcall(rd78x00_pci_init);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
80*4882a593Smuzhiyun /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
81*4882a593Smuzhiyun .atag_offset = 0x100,
82*4882a593Smuzhiyun .nr_irqs = MV78XX0_NR_IRQS,
83*4882a593Smuzhiyun .init_machine = rd78x00_masa_init,
84*4882a593Smuzhiyun .map_io = mv78xx0_map_io,
85*4882a593Smuzhiyun .init_early = mv78xx0_init_early,
86*4882a593Smuzhiyun .init_irq = mv78xx0_init_irq,
87*4882a593Smuzhiyun .init_time = mv78xx0_timer_init,
88*4882a593Smuzhiyun .restart = mv78xx0_restart,
89*4882a593Smuzhiyun MACHINE_END
90