1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * IRQ definitions for Marvell MV78xx0 SoCs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_IRQS_H 10*4882a593Smuzhiyun #define __ASM_ARCH_IRQS_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * MV78xx0 Low Interrupt Controller 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define IRQ_MV78XX0_ERR 0 16*4882a593Smuzhiyun #define IRQ_MV78XX0_SPI 1 17*4882a593Smuzhiyun #define IRQ_MV78XX0_I2C_0 2 18*4882a593Smuzhiyun #define IRQ_MV78XX0_I2C_1 3 19*4882a593Smuzhiyun #define IRQ_MV78XX0_IDMA_0 4 20*4882a593Smuzhiyun #define IRQ_MV78XX0_IDMA_1 5 21*4882a593Smuzhiyun #define IRQ_MV78XX0_IDMA_2 6 22*4882a593Smuzhiyun #define IRQ_MV78XX0_IDMA_3 7 23*4882a593Smuzhiyun #define IRQ_MV78XX0_TIMER_0 8 24*4882a593Smuzhiyun #define IRQ_MV78XX0_TIMER_1 9 25*4882a593Smuzhiyun #define IRQ_MV78XX0_TIMER_2 10 26*4882a593Smuzhiyun #define IRQ_MV78XX0_TIMER_3 11 27*4882a593Smuzhiyun #define IRQ_MV78XX0_UART_0 12 28*4882a593Smuzhiyun #define IRQ_MV78XX0_UART_1 13 29*4882a593Smuzhiyun #define IRQ_MV78XX0_UART_2 14 30*4882a593Smuzhiyun #define IRQ_MV78XX0_UART_3 15 31*4882a593Smuzhiyun #define IRQ_MV78XX0_USB_0 16 32*4882a593Smuzhiyun #define IRQ_MV78XX0_USB_1 17 33*4882a593Smuzhiyun #define IRQ_MV78XX0_USB_2 18 34*4882a593Smuzhiyun #define IRQ_MV78XX0_CRYPTO 19 35*4882a593Smuzhiyun #define IRQ_MV78XX0_SDIO_0 20 36*4882a593Smuzhiyun #define IRQ_MV78XX0_SDIO_1 21 37*4882a593Smuzhiyun #define IRQ_MV78XX0_XOR_0 22 38*4882a593Smuzhiyun #define IRQ_MV78XX0_XOR_1 23 39*4882a593Smuzhiyun #define IRQ_MV78XX0_I2S_0 24 40*4882a593Smuzhiyun #define IRQ_MV78XX0_I2S_1 25 41*4882a593Smuzhiyun #define IRQ_MV78XX0_SATA 26 42*4882a593Smuzhiyun #define IRQ_MV78XX0_TDMI 27 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * MV78xx0 High Interrupt Controller 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_00 32 48*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_01 33 49*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_02 34 50*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_03 35 51*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_10 36 52*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_11 37 53*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_12 38 54*4882a593Smuzhiyun #define IRQ_MV78XX0_PCIE_13 39 55*4882a593Smuzhiyun #define IRQ_MV78XX0_GE00_SUM 40 56*4882a593Smuzhiyun #define IRQ_MV78XX0_GE00_RX 41 57*4882a593Smuzhiyun #define IRQ_MV78XX0_GE00_TX 42 58*4882a593Smuzhiyun #define IRQ_MV78XX0_GE00_MISC 43 59*4882a593Smuzhiyun #define IRQ_MV78XX0_GE01_SUM 44 60*4882a593Smuzhiyun #define IRQ_MV78XX0_GE01_RX 45 61*4882a593Smuzhiyun #define IRQ_MV78XX0_GE01_TX 46 62*4882a593Smuzhiyun #define IRQ_MV78XX0_GE01_MISC 47 63*4882a593Smuzhiyun #define IRQ_MV78XX0_GE10_SUM 48 64*4882a593Smuzhiyun #define IRQ_MV78XX0_GE10_RX 49 65*4882a593Smuzhiyun #define IRQ_MV78XX0_GE10_TX 50 66*4882a593Smuzhiyun #define IRQ_MV78XX0_GE10_MISC 51 67*4882a593Smuzhiyun #define IRQ_MV78XX0_GE11_SUM 52 68*4882a593Smuzhiyun #define IRQ_MV78XX0_GE11_RX 53 69*4882a593Smuzhiyun #define IRQ_MV78XX0_GE11_TX 54 70*4882a593Smuzhiyun #define IRQ_MV78XX0_GE11_MISC 55 71*4882a593Smuzhiyun #define IRQ_MV78XX0_GPIO_0_7 56 72*4882a593Smuzhiyun #define IRQ_MV78XX0_GPIO_8_15 57 73*4882a593Smuzhiyun #define IRQ_MV78XX0_GPIO_16_23 58 74*4882a593Smuzhiyun #define IRQ_MV78XX0_GPIO_24_31 59 75*4882a593Smuzhiyun #define IRQ_MV78XX0_DB_IN 60 76*4882a593Smuzhiyun #define IRQ_MV78XX0_DB_OUT 61 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * MV78xx0 Error Interrupt Controller 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun #define IRQ_MV78XX0_GE_ERR 70 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * MV78XX0 General Purpose Pins 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun #define IRQ_MV78XX0_GPIO_START 96 87*4882a593Smuzhiyun #define NR_GPIO_IRQS 32 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif 93