1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-mv78xx0/irq.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * MV78xx0 IRQ handling.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/gpio.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <asm/exception.h>
15*4882a593Smuzhiyun #include <plat/orion-gpio.h>
16*4882a593Smuzhiyun #include <plat/irq.h>
17*4882a593Smuzhiyun #include "bridge-regs.h"
18*4882a593Smuzhiyun #include "common.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static int __initdata gpio0_irqs[4] = {
21*4882a593Smuzhiyun IRQ_MV78XX0_GPIO_0_7,
22*4882a593Smuzhiyun IRQ_MV78XX0_GPIO_8_15,
23*4882a593Smuzhiyun IRQ_MV78XX0_GPIO_16_23,
24*4882a593Smuzhiyun IRQ_MV78XX0_GPIO_24_31,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static asmlinkage void
mv78xx0_legacy_handle_irq(struct pt_regs * regs)30*4882a593Smuzhiyun __exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun u32 stat;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
35*4882a593Smuzhiyun stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
36*4882a593Smuzhiyun if (stat) {
37*4882a593Smuzhiyun unsigned int hwirq = __fls(stat);
38*4882a593Smuzhiyun handle_IRQ(hwirq, regs);
39*4882a593Smuzhiyun return;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
42*4882a593Smuzhiyun stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
43*4882a593Smuzhiyun if (stat) {
44*4882a593Smuzhiyun unsigned int hwirq = 32 + __fls(stat);
45*4882a593Smuzhiyun handle_IRQ(hwirq, regs);
46*4882a593Smuzhiyun return;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
49*4882a593Smuzhiyun stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
50*4882a593Smuzhiyun if (stat) {
51*4882a593Smuzhiyun unsigned int hwirq = 64 + __fls(stat);
52*4882a593Smuzhiyun handle_IRQ(hwirq, regs);
53*4882a593Smuzhiyun return;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
mv78xx0_init_irq(void)57*4882a593Smuzhiyun void __init mv78xx0_init_irq(void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
60*4882a593Smuzhiyun orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
61*4882a593Smuzhiyun orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun set_handle_irq(mv78xx0_legacy_handle_irq);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
67*4882a593Smuzhiyun * registers for core #1 are at an offset of 0x18 from those of
68*4882a593Smuzhiyun * core #0.)
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
71*4882a593Smuzhiyun mv78xx0_core_index() ? 0x18 : 0,
72*4882a593Smuzhiyun IRQ_MV78XX0_GPIO_START, gpio0_irqs);
73*4882a593Smuzhiyun }
74