1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Marvell DB-78x00-BP Development Board Setup
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/ata_platform.h>
15*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
16*4882a593Smuzhiyun #include <linux/ethtool.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <asm/mach-types.h>
19*4882a593Smuzhiyun #include <asm/mach/arch.h>
20*4882a593Smuzhiyun #include "mv78xx0.h"
21*4882a593Smuzhiyun #include "common.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static struct mv643xx_eth_platform_data db78x00_ge00_data = {
24*4882a593Smuzhiyun .phy_addr = MV643XX_ETH_PHY_ADDR(8),
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static struct mv643xx_eth_platform_data db78x00_ge01_data = {
28*4882a593Smuzhiyun .phy_addr = MV643XX_ETH_PHY_ADDR(9),
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static struct mv643xx_eth_platform_data db78x00_ge10_data = {
32*4882a593Smuzhiyun .phy_addr = MV643XX_ETH_PHY_ADDR(10),
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static struct mv643xx_eth_platform_data db78x00_ge11_data = {
36*4882a593Smuzhiyun .phy_addr = MV643XX_ETH_PHY_ADDR(11),
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static struct mv_sata_platform_data db78x00_sata_data = {
40*4882a593Smuzhiyun .n_ports = 2,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static struct i2c_board_info __initdata db78x00_i2c_rtc = {
44*4882a593Smuzhiyun I2C_BOARD_INFO("ds1338", 0x68),
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun
db78x00_init(void)48*4882a593Smuzhiyun static void __init db78x00_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * Basic MV78xx0 setup. Needs to be called early.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun mv78xx0_init();
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Partition on-chip peripherals between the two CPU cores.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun if (mv78xx0_core_index() == 0) {
59*4882a593Smuzhiyun mv78xx0_ehci0_init();
60*4882a593Smuzhiyun mv78xx0_ehci1_init();
61*4882a593Smuzhiyun mv78xx0_ehci2_init();
62*4882a593Smuzhiyun mv78xx0_ge00_init(&db78x00_ge00_data);
63*4882a593Smuzhiyun mv78xx0_ge01_init(&db78x00_ge01_data);
64*4882a593Smuzhiyun mv78xx0_ge10_init(&db78x00_ge10_data);
65*4882a593Smuzhiyun mv78xx0_ge11_init(&db78x00_ge11_data);
66*4882a593Smuzhiyun mv78xx0_sata_init(&db78x00_sata_data);
67*4882a593Smuzhiyun mv78xx0_uart0_init();
68*4882a593Smuzhiyun mv78xx0_uart2_init();
69*4882a593Smuzhiyun mv78xx0_i2c_init();
70*4882a593Smuzhiyun i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
71*4882a593Smuzhiyun } else {
72*4882a593Smuzhiyun mv78xx0_uart1_init();
73*4882a593Smuzhiyun mv78xx0_uart3_init();
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
db78x00_pci_init(void)77*4882a593Smuzhiyun static int __init db78x00_pci_init(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun if (machine_is_db78x00_bp()) {
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * Assign the x16 PCIe slot on the board to CPU core
82*4882a593Smuzhiyun * #0, and let CPU core #1 have the four x1 slots.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun if (mv78xx0_core_index() == 0)
85*4882a593Smuzhiyun mv78xx0_pcie_init(0, 1);
86*4882a593Smuzhiyun else
87*4882a593Smuzhiyun mv78xx0_pcie_init(1, 0);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun subsys_initcall(db78x00_pci_init);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
95*4882a593Smuzhiyun /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
96*4882a593Smuzhiyun .atag_offset = 0x100,
97*4882a593Smuzhiyun .nr_irqs = MV78XX0_NR_IRQS,
98*4882a593Smuzhiyun .init_machine = db78x00_init,
99*4882a593Smuzhiyun .map_io = mv78xx0_map_io,
100*4882a593Smuzhiyun .init_early = mv78xx0_init_early,
101*4882a593Smuzhiyun .init_irq = mv78xx0_init_irq,
102*4882a593Smuzhiyun .init_time = mv78xx0_timer_init,
103*4882a593Smuzhiyun .restart = mv78xx0_restart,
104*4882a593Smuzhiyun MACHINE_END
105