1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 3*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 4*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARCH_BRIDGE_REGS_H 8*4882a593Smuzhiyun #define __ASM_ARCH_BRIDGE_REGS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "mv78xx0.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) 13*4882a593Smuzhiyun #define L2_WRITETHROUGH 0x00020000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) 16*4882a593Smuzhiyun #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) 17*4882a593Smuzhiyun #define SOFT_RESET_OUT_EN 0x00000004 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) 20*4882a593Smuzhiyun #define SOFT_RESET 0x00000001 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define BRIDGE_INT_TIMER1_CLR (~0x0004) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) 25*4882a593Smuzhiyun #define IRQ_CAUSE_ERR_OFF 0x0000 26*4882a593Smuzhiyun #define IRQ_CAUSE_LOW_OFF 0x0004 27*4882a593Smuzhiyun #define IRQ_CAUSE_HIGH_OFF 0x0008 28*4882a593Smuzhiyun #define IRQ_MASK_ERR_OFF 0x000c 29*4882a593Smuzhiyun #define IRQ_MASK_LOW_OFF 0x0010 30*4882a593Smuzhiyun #define IRQ_MASK_HIGH_OFF 0x0014 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) 33*4882a593Smuzhiyun #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36