1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Device Tree support for MStar/Sigmastar Armv7 SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2020 thingy.jp
6*4882a593Smuzhiyun * Author: Daniel Palmer <daniel@thingy.jp>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <asm/mach/arch.h>
11*4882a593Smuzhiyun #include <asm/mach/map.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * In the u-boot code the area these registers are in is
18*4882a593Smuzhiyun * called "L3 bridge" and there are register descriptions
19*4882a593Smuzhiyun * for something in the same area called "AXI".
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * It's not exactly known what this is but the vendor code
22*4882a593Smuzhiyun * for both u-boot and linux share calls to "flush the miu pipe".
23*4882a593Smuzhiyun * This seems to be to force pending CPU writes to memory so that
24*4882a593Smuzhiyun * the state is right before DMA capable devices try to read
25*4882a593Smuzhiyun * descriptors and data the CPU has prepared. Without doing this
26*4882a593Smuzhiyun * ethernet doesn't work reliably for example.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define MSTARV7_L3BRIDGE_FLUSH 0x14
30*4882a593Smuzhiyun #define MSTARV7_L3BRIDGE_STATUS 0x40
31*4882a593Smuzhiyun #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0)
32*4882a593Smuzhiyun #define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static void __iomem *l3bridge;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static const char * const mstarv7_board_dt_compat[] __initconst = {
37*4882a593Smuzhiyun "mstar,infinity",
38*4882a593Smuzhiyun "mstar,infinity3",
39*4882a593Smuzhiyun "mstar,mercury5",
40*4882a593Smuzhiyun NULL,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * This may need locking to deal with situations where an interrupt
45*4882a593Smuzhiyun * happens while we are in here and mb() gets called by the interrupt handler.
46*4882a593Smuzhiyun *
47*4882a593Smuzhiyun * The vendor code did have a spin lock but it doesn't seem to be needed and
48*4882a593Smuzhiyun * removing it hasn't caused any side effects so far.
49*4882a593Smuzhiyun *
50*4882a593Smuzhiyun * [writel|readl]_relaxed have to be used here because otherwise
51*4882a593Smuzhiyun * we'd end up right back in here.
52*4882a593Smuzhiyun */
mstarv7_mb(void)53*4882a593Smuzhiyun static void mstarv7_mb(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun /* toggle the flush miu pipe fire bit */
56*4882a593Smuzhiyun writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
57*4882a593Smuzhiyun writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
58*4882a593Smuzhiyun + MSTARV7_L3BRIDGE_FLUSH);
59*4882a593Smuzhiyun while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS)
60*4882a593Smuzhiyun & MSTARV7_L3BRIDGE_STATUS_DONE)) {
61*4882a593Smuzhiyun /* wait for flush to complete */
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
mstarv7_init(void)65*4882a593Smuzhiyun static void __init mstarv7_init(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct device_node *np;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge");
70*4882a593Smuzhiyun l3bridge = of_iomap(np, 0);
71*4882a593Smuzhiyun if (l3bridge)
72*4882a593Smuzhiyun soc_mb = mstarv7_mb;
73*4882a593Smuzhiyun else
74*4882a593Smuzhiyun pr_warn("Failed to install memory barrier, DMA will be broken!\n");
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
78*4882a593Smuzhiyun .dt_compat = mstarv7_board_dt_compat,
79*4882a593Smuzhiyun .init_machine = mstarv7_init,
80*4882a593Smuzhiyun MACHINE_END
81