1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Application Subsystem Power Management Unit 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ASM_MACH_REGS_APMU_H 7*4882a593Smuzhiyun #define __ASM_MACH_REGS_APMU_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "addr-map.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define APMU_FNCLK_EN (1 << 4) 12*4882a593Smuzhiyun #define APMU_AXICLK_EN (1 << 3) 13*4882a593Smuzhiyun #define APMU_FNRST_DIS (1 << 1) 14*4882a593Smuzhiyun #define APMU_AXIRST_DIS (1 << 0) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Wake Clear Register */ 17*4882a593Smuzhiyun #define APMU_WAKE_CLR APMU_REG(0x07c) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define APMU_PXA168_KP_WAKE_CLR (1 << 7) 20*4882a593Smuzhiyun #define APMU_PXA168_CFI_WAKE_CLR (1 << 6) 21*4882a593Smuzhiyun #define APMU_PXA168_XD_WAKE_CLR (1 << 5) 22*4882a593Smuzhiyun #define APMU_PXA168_MSP_WAKE_CLR (1 << 4) 23*4882a593Smuzhiyun #define APMU_PXA168_SD4_WAKE_CLR (1 << 3) 24*4882a593Smuzhiyun #define APMU_PXA168_SD3_WAKE_CLR (1 << 2) 25*4882a593Smuzhiyun #define APMU_PXA168_SD2_WAKE_CLR (1 << 1) 26*4882a593Smuzhiyun #define APMU_PXA168_SD1_WAKE_CLR (1 << 0) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* __ASM_MACH_REGS_APMU_H */ 29