1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * PXA910 Power Management Routines 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2009 Marvell International Ltd. 6*4882a593Smuzhiyun * All Rights Reserved 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __PXA910_PM_H__ 10*4882a593Smuzhiyun #define __PXA910_PM_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG APMU_REG(0x0018) 13*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1) 14*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5) 15*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6) 16*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16) 17*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18) 18*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21) 19*4882a593Smuzhiyun #define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c) 22*4882a593Smuzhiyun #define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define MPMU_FCCR MPMU_REG(0x0008) 25*4882a593Smuzhiyun #define MPMU_APCR MPMU_REG(0x1000) 26*4882a593Smuzhiyun #define MPMU_APCR_AXISD (1 << 31) 27*4882a593Smuzhiyun #define MPMU_APCR_DSPSD (1 << 30) 28*4882a593Smuzhiyun #define MPMU_APCR_SLPEN (1 << 29) 29*4882a593Smuzhiyun #define MPMU_APCR_DTCMSD (1 << 28) 30*4882a593Smuzhiyun #define MPMU_APCR_DDRCORSD (1 << 27) 31*4882a593Smuzhiyun #define MPMU_APCR_APBSD (1 << 26) 32*4882a593Smuzhiyun #define MPMU_APCR_BBSD (1 << 25) 33*4882a593Smuzhiyun #define MPMU_APCR_SLPWP0 (1 << 23) 34*4882a593Smuzhiyun #define MPMU_APCR_SLPWP1 (1 << 22) 35*4882a593Smuzhiyun #define MPMU_APCR_SLPWP2 (1 << 21) 36*4882a593Smuzhiyun #define MPMU_APCR_SLPWP3 (1 << 20) 37*4882a593Smuzhiyun #define MPMU_APCR_VCTCXOSD (1 << 19) 38*4882a593Smuzhiyun #define MPMU_APCR_SLPWP4 (1 << 18) 39*4882a593Smuzhiyun #define MPMU_APCR_SLPWP5 (1 << 17) 40*4882a593Smuzhiyun #define MPMU_APCR_SLPWP6 (1 << 16) 41*4882a593Smuzhiyun #define MPMU_APCR_SLPWP7 (1 << 15) 42*4882a593Smuzhiyun #define MPMU_APCR_MSASLPEN (1 << 14) 43*4882a593Smuzhiyun #define MPMU_APCR_STBYEN (1 << 13) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MPMU_AWUCRM MPMU_REG(0x104c) 46*4882a593Smuzhiyun #define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25) 47*4882a593Smuzhiyun #define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24) 48*4882a593Smuzhiyun #define MPMU_AWUCRM_SDH1 (1 << 23) 49*4882a593Smuzhiyun #define MPMU_AWUCRM_SDH2 (1 << 22) 50*4882a593Smuzhiyun #define MPMU_AWUCRM_KEYPRESS (1 << 21) 51*4882a593Smuzhiyun #define MPMU_AWUCRM_TRACKBALL (1 << 20) 52*4882a593Smuzhiyun #define MPMU_AWUCRM_NEWROTARY (1 << 19) 53*4882a593Smuzhiyun #define MPMU_AWUCRM_RTC_ALARM (1 << 17) 54*4882a593Smuzhiyun #define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13) 55*4882a593Smuzhiyun #define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12) 56*4882a593Smuzhiyun #define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11) 57*4882a593Smuzhiyun #define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10) 58*4882a593Smuzhiyun #define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9) 59*4882a593Smuzhiyun #define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8) 60*4882a593Smuzhiyun #define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7)) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun enum { 63*4882a593Smuzhiyun POWER_MODE_ACTIVE = 0, 64*4882a593Smuzhiyun POWER_MODE_CORE_INTIDLE, 65*4882a593Smuzhiyun POWER_MODE_CORE_EXTIDLE, 66*4882a593Smuzhiyun POWER_MODE_APPS_IDLE, 67*4882a593Smuzhiyun POWER_MODE_APPS_SLEEP, 68*4882a593Smuzhiyun POWER_MODE_SYS_SLEEP, 69*4882a593Smuzhiyun POWER_MODE_HIBERNATE, 70*4882a593Smuzhiyun POWER_MODE_UDR, 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun extern int pxa910_set_wake(struct irq_data *data, unsigned int on); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif 76