1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * MMP2 Power Management Routines 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2010 Marvell International Ltd. 6*4882a593Smuzhiyun * All Rights Reserved 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MMP2_PM_H__ 10*4882a593Smuzhiyun #define __MMP2_PM_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "addr-map.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define APMU_PJ_IDLE_CFG APMU_REG(0x018) 15*4882a593Smuzhiyun #define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) 16*4882a593Smuzhiyun #define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) 17*4882a593Smuzhiyun #define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) 18*4882a593Smuzhiyun #define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) 19*4882a593Smuzhiyun #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define APMU_SRAM_PWR_DWN APMU_REG(0x08c) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MPMU_SCCR MPMU_REG(0x038) 24*4882a593Smuzhiyun #define MPMU_PCR_PJ MPMU_REG(0x1000) 25*4882a593Smuzhiyun #define MPMU_PCR_PJ_AXISD (1 << 31) 26*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPEN (1 << 29) 27*4882a593Smuzhiyun #define MPMU_PCR_PJ_SPSD (1 << 28) 28*4882a593Smuzhiyun #define MPMU_PCR_PJ_DDRCORSD (1 << 27) 29*4882a593Smuzhiyun #define MPMU_PCR_PJ_APBSD (1 << 26) 30*4882a593Smuzhiyun #define MPMU_PCR_PJ_INTCLR (1 << 24) 31*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP0 (1 << 23) 32*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP1 (1 << 22) 33*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP2 (1 << 21) 34*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP3 (1 << 20) 35*4882a593Smuzhiyun #define MPMU_PCR_PJ_VCTCXOSD (1 << 19) 36*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP4 (1 << 18) 37*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP5 (1 << 17) 38*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP6 (1 << 16) 39*4882a593Smuzhiyun #define MPMU_PCR_PJ_SLPWP7 (1 << 15) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) 42*4882a593Smuzhiyun #define MPMU_CGR_PJ MPMU_REG(0x1024) 43*4882a593Smuzhiyun #define MPMU_WUCRM_PJ MPMU_REG(0x104c) 44*4882a593Smuzhiyun #define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) 45*4882a593Smuzhiyun #define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun enum { 48*4882a593Smuzhiyun POWER_MODE_ACTIVE = 0, 49*4882a593Smuzhiyun POWER_MODE_CORE_INTIDLE, 50*4882a593Smuzhiyun POWER_MODE_CORE_EXTIDLE, 51*4882a593Smuzhiyun POWER_MODE_APPS_IDLE, 52*4882a593Smuzhiyun POWER_MODE_APPS_SLEEP, 53*4882a593Smuzhiyun POWER_MODE_CHIP_SLEEP, 54*4882a593Smuzhiyun POWER_MODE_SYS_SLEEP, 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun extern void mmp2_pm_enter_lowpower_mode(int state); 58*4882a593Smuzhiyun extern int mmp2_set_wake(struct irq_data *d, unsigned int on); 59*4882a593Smuzhiyun #endif 60