xref: /OK3568_Linux_fs/kernel/arch/arm/mach-mmp/mmp2.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * linux/arch/arm/mach-mmp/mmp2.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * code name MMP2
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2009 Marvell International Ltd.
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun #include <linux/clk/mmp.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/irqchip/mmp.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <asm/hardware/cache-tauros2.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <asm/mach/time.h>
21*4882a593Smuzhiyun #include "addr-map.h"
22*4882a593Smuzhiyun #include "regs-apbc.h"
23*4882a593Smuzhiyun #include <linux/soc/mmp/cputype.h>
24*4882a593Smuzhiyun #include "irqs.h"
25*4882a593Smuzhiyun #include "mfp.h"
26*4882a593Smuzhiyun #include "devices.h"
27*4882a593Smuzhiyun #include "mmp2.h"
28*4882a593Smuzhiyun #include "pm-mmp2.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include "common.h"
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define MFPR_VIRT_BASE	(APB_VIRT_BASE + 0x1e000)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static struct mfp_addr_map mmp2_addr_map[] __initdata = {
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO0, GPIO58, 0x54),
37*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO59, GPIO73, 0x280),
38*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO74, GPIO101, 0x170),
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	MFP_ADDR(GPIO102, 0x0),
41*4882a593Smuzhiyun 	MFP_ADDR(GPIO103, 0x4),
42*4882a593Smuzhiyun 	MFP_ADDR(GPIO104, 0x1fc),
43*4882a593Smuzhiyun 	MFP_ADDR(GPIO105, 0x1f8),
44*4882a593Smuzhiyun 	MFP_ADDR(GPIO106, 0x1f4),
45*4882a593Smuzhiyun 	MFP_ADDR(GPIO107, 0x1f0),
46*4882a593Smuzhiyun 	MFP_ADDR(GPIO108, 0x21c),
47*4882a593Smuzhiyun 	MFP_ADDR(GPIO109, 0x218),
48*4882a593Smuzhiyun 	MFP_ADDR(GPIO110, 0x214),
49*4882a593Smuzhiyun 	MFP_ADDR(GPIO111, 0x200),
50*4882a593Smuzhiyun 	MFP_ADDR(GPIO112, 0x244),
51*4882a593Smuzhiyun 	MFP_ADDR(GPIO113, 0x25c),
52*4882a593Smuzhiyun 	MFP_ADDR(GPIO114, 0x164),
53*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO115, GPIO122, 0x260),
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	MFP_ADDR(GPIO123, 0x148),
56*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO124, GPIO141, 0xc),
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	MFP_ADDR(GPIO142, 0x8),
59*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO143, GPIO151, 0x220),
60*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO152, GPIO153, 0x248),
61*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO154, GPIO155, 0x254),
62*4882a593Smuzhiyun 	MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	MFP_ADDR(GPIO160, 0x250),
65*4882a593Smuzhiyun 	MFP_ADDR(GPIO161, 0x210),
66*4882a593Smuzhiyun 	MFP_ADDR(GPIO162, 0x20c),
67*4882a593Smuzhiyun 	MFP_ADDR(GPIO163, 0x208),
68*4882a593Smuzhiyun 	MFP_ADDR(GPIO164, 0x204),
69*4882a593Smuzhiyun 	MFP_ADDR(GPIO165, 0x1ec),
70*4882a593Smuzhiyun 	MFP_ADDR(GPIO166, 0x1e8),
71*4882a593Smuzhiyun 	MFP_ADDR(GPIO167, 0x1e4),
72*4882a593Smuzhiyun 	MFP_ADDR(GPIO168, 0x1e0),
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
75*4882a593Smuzhiyun 	MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	MFP_ADDR(PMIC_INT, 0x2c4),
78*4882a593Smuzhiyun 	MFP_ADDR(CLK_REQ, 0x160),
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	MFP_ADDR_END,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
mmp2_clear_pmic_int(void)83*4882a593Smuzhiyun void mmp2_clear_pmic_int(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	void __iomem *mfpr_pmic;
86*4882a593Smuzhiyun 	unsigned long data;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
89*4882a593Smuzhiyun 	data = __raw_readl(mfpr_pmic);
90*4882a593Smuzhiyun 	__raw_writel(data | (1 << 6), mfpr_pmic);
91*4882a593Smuzhiyun 	__raw_writel(data, mfpr_pmic);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
mmp2_init_irq(void)94*4882a593Smuzhiyun void __init mmp2_init_irq(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	mmp2_init_icu();
97*4882a593Smuzhiyun #ifdef CONFIG_PM
98*4882a593Smuzhiyun 	icu_irq_chip.irq_set_wake = mmp2_set_wake;
99*4882a593Smuzhiyun #endif
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
mmp2_init(void)102*4882a593Smuzhiyun static int __init mmp2_init(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	if (cpu_is_mmp2()) {
105*4882a593Smuzhiyun #ifdef CONFIG_CACHE_TAUROS2
106*4882a593Smuzhiyun 		tauros2_init(0);
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun 		mfp_init_base(MFPR_VIRT_BASE);
109*4882a593Smuzhiyun 		mfp_init_addr(mmp2_addr_map);
110*4882a593Smuzhiyun 		mmp2_clk_init(APB_PHYS_BASE + 0x50000,
111*4882a593Smuzhiyun 			      AXI_PHYS_BASE + 0x82800,
112*4882a593Smuzhiyun 			      APB_PHYS_BASE + 0x15000);
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun postcore_initcall(mmp2_init);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun #define APBC_TIMERS	APBC_REG(0x024)
120*4882a593Smuzhiyun 
mmp2_timer_init(void)121*4882a593Smuzhiyun void __init mmp2_timer_init(void)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	unsigned long clk_rst;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	/*
128*4882a593Smuzhiyun 	 * enable bus/functional clock, enable 6.5MHz (divider 4),
129*4882a593Smuzhiyun 	 * release reset
130*4882a593Smuzhiyun 	 */
131*4882a593Smuzhiyun 	clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
132*4882a593Smuzhiyun 	__raw_writel(clk_rst, APBC_TIMERS);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	mmp_timer_init(IRQ_MMP2_TIMER1, 6500000);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /* on-chip devices */
138*4882a593Smuzhiyun MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
139*4882a593Smuzhiyun MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
140*4882a593Smuzhiyun MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
141*4882a593Smuzhiyun MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
142*4882a593Smuzhiyun MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
143*4882a593Smuzhiyun MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
144*4882a593Smuzhiyun MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
145*4882a593Smuzhiyun MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
146*4882a593Smuzhiyun MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
147*4882a593Smuzhiyun MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
148*4882a593Smuzhiyun MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
149*4882a593Smuzhiyun MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
150*4882a593Smuzhiyun MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
151*4882a593Smuzhiyun MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
152*4882a593Smuzhiyun MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
153*4882a593Smuzhiyun MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
154*4882a593Smuzhiyun /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
155*4882a593Smuzhiyun MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun struct resource mmp2_resource_gpio[] = {
158*4882a593Smuzhiyun 	{
159*4882a593Smuzhiyun 		.start	= 0xd4019000,
160*4882a593Smuzhiyun 		.end	= 0xd4019fff,
161*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
162*4882a593Smuzhiyun 	}, {
163*4882a593Smuzhiyun 		.start	= IRQ_MMP2_GPIO,
164*4882a593Smuzhiyun 		.end	= IRQ_MMP2_GPIO,
165*4882a593Smuzhiyun 		.name	= "gpio_mux",
166*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ,
167*4882a593Smuzhiyun 	},
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun struct platform_device mmp2_device_gpio = {
171*4882a593Smuzhiyun 	.name		= "mmp2-gpio",
172*4882a593Smuzhiyun 	.id		= -1,
173*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(mmp2_resource_gpio),
174*4882a593Smuzhiyun 	.resource	= mmp2_resource_gpio,
175*4882a593Smuzhiyun };
176