1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/arm/mach-mmp/jasper.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Support for the Marvell Jasper Development Platform.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2009-2010 Marvell International Ltd.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/gpio-pxa.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/regulator/machine.h>
16*4882a593Smuzhiyun #include <linux/regulator/max8649.h>
17*4882a593Smuzhiyun #include <linux/mfd/max8925.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "irqs.h"
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/mach/arch.h>
23*4882a593Smuzhiyun #include "addr-map.h"
24*4882a593Smuzhiyun #include "mfp-mmp2.h"
25*4882a593Smuzhiyun #include "mmp2.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "common.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define JASPER_NR_IRQS (MMP_NR_IRQS + 48)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static unsigned long jasper_pin_config[] __initdata = {
32*4882a593Smuzhiyun /* UART1 */
33*4882a593Smuzhiyun GPIO29_UART1_RXD,
34*4882a593Smuzhiyun GPIO30_UART1_TXD,
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* UART3 */
37*4882a593Smuzhiyun GPIO51_UART3_RXD,
38*4882a593Smuzhiyun GPIO52_UART3_TXD,
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* DFI */
41*4882a593Smuzhiyun GPIO168_DFI_D0,
42*4882a593Smuzhiyun GPIO167_DFI_D1,
43*4882a593Smuzhiyun GPIO166_DFI_D2,
44*4882a593Smuzhiyun GPIO165_DFI_D3,
45*4882a593Smuzhiyun GPIO107_DFI_D4,
46*4882a593Smuzhiyun GPIO106_DFI_D5,
47*4882a593Smuzhiyun GPIO105_DFI_D6,
48*4882a593Smuzhiyun GPIO104_DFI_D7,
49*4882a593Smuzhiyun GPIO111_DFI_D8,
50*4882a593Smuzhiyun GPIO164_DFI_D9,
51*4882a593Smuzhiyun GPIO163_DFI_D10,
52*4882a593Smuzhiyun GPIO162_DFI_D11,
53*4882a593Smuzhiyun GPIO161_DFI_D12,
54*4882a593Smuzhiyun GPIO110_DFI_D13,
55*4882a593Smuzhiyun GPIO109_DFI_D14,
56*4882a593Smuzhiyun GPIO108_DFI_D15,
57*4882a593Smuzhiyun GPIO143_ND_nCS0,
58*4882a593Smuzhiyun GPIO144_ND_nCS1,
59*4882a593Smuzhiyun GPIO147_ND_nWE,
60*4882a593Smuzhiyun GPIO148_ND_nRE,
61*4882a593Smuzhiyun GPIO150_ND_ALE,
62*4882a593Smuzhiyun GPIO149_ND_CLE,
63*4882a593Smuzhiyun GPIO112_ND_RDY0,
64*4882a593Smuzhiyun GPIO160_ND_RDY1,
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* PMIC */
67*4882a593Smuzhiyun PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* MMC1 */
70*4882a593Smuzhiyun GPIO131_MMC1_DAT3,
71*4882a593Smuzhiyun GPIO132_MMC1_DAT2,
72*4882a593Smuzhiyun GPIO133_MMC1_DAT1,
73*4882a593Smuzhiyun GPIO134_MMC1_DAT0,
74*4882a593Smuzhiyun GPIO136_MMC1_CMD,
75*4882a593Smuzhiyun GPIO139_MMC1_CLK,
76*4882a593Smuzhiyun GPIO140_MMC1_CD,
77*4882a593Smuzhiyun GPIO141_MMC1_WP,
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* MMC2 */
80*4882a593Smuzhiyun GPIO37_MMC2_DAT3,
81*4882a593Smuzhiyun GPIO38_MMC2_DAT2,
82*4882a593Smuzhiyun GPIO39_MMC2_DAT1,
83*4882a593Smuzhiyun GPIO40_MMC2_DAT0,
84*4882a593Smuzhiyun GPIO41_MMC2_CMD,
85*4882a593Smuzhiyun GPIO42_MMC2_CLK,
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* MMC3 */
88*4882a593Smuzhiyun GPIO165_MMC3_DAT7,
89*4882a593Smuzhiyun GPIO162_MMC3_DAT6,
90*4882a593Smuzhiyun GPIO166_MMC3_DAT5,
91*4882a593Smuzhiyun GPIO163_MMC3_DAT4,
92*4882a593Smuzhiyun GPIO167_MMC3_DAT3,
93*4882a593Smuzhiyun GPIO164_MMC3_DAT2,
94*4882a593Smuzhiyun GPIO168_MMC3_DAT1,
95*4882a593Smuzhiyun GPIO111_MMC3_DAT0,
96*4882a593Smuzhiyun GPIO112_MMC3_CMD,
97*4882a593Smuzhiyun GPIO151_MMC3_CLK,
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
101*4882a593Smuzhiyun .irq_base = MMP_GPIO_TO_IRQ(0),
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static struct regulator_consumer_supply max8649_supply[] = {
105*4882a593Smuzhiyun REGULATOR_SUPPLY("vcc_core", NULL),
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static struct regulator_init_data max8649_init_data = {
109*4882a593Smuzhiyun .constraints = {
110*4882a593Smuzhiyun .name = "vcc_core range",
111*4882a593Smuzhiyun .min_uV = 1150000,
112*4882a593Smuzhiyun .max_uV = 1280000,
113*4882a593Smuzhiyun .always_on = 1,
114*4882a593Smuzhiyun .boot_on = 1,
115*4882a593Smuzhiyun .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
116*4882a593Smuzhiyun },
117*4882a593Smuzhiyun .num_consumer_supplies = 1,
118*4882a593Smuzhiyun .consumer_supplies = &max8649_supply[0],
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static struct max8649_platform_data jasper_max8649_info = {
122*4882a593Smuzhiyun .mode = 2, /* VID1 = 1, VID0 = 0 */
123*4882a593Smuzhiyun .extclk = 0,
124*4882a593Smuzhiyun .ramp_timing = MAX8649_RAMP_32MV,
125*4882a593Smuzhiyun .regulator = &max8649_init_data,
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static struct max8925_backlight_pdata jasper_backlight_data = {
129*4882a593Smuzhiyun .dual_string = 0,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun static struct max8925_power_pdata jasper_power_data = {
133*4882a593Smuzhiyun .batt_detect = 0, /* can't detect battery by ID pin */
134*4882a593Smuzhiyun .topoff_threshold = MAX8925_TOPOFF_THR_10PER,
135*4882a593Smuzhiyun .fast_charge = MAX8925_FCHG_1000MA,
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static struct max8925_platform_data jasper_max8925_info = {
139*4882a593Smuzhiyun .backlight = &jasper_backlight_data,
140*4882a593Smuzhiyun .power = &jasper_power_data,
141*4882a593Smuzhiyun .irq_base = MMP_NR_IRQS,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun static struct i2c_board_info jasper_twsi1_info[] = {
145*4882a593Smuzhiyun [0] = {
146*4882a593Smuzhiyun .type = "max8649",
147*4882a593Smuzhiyun .addr = 0x60,
148*4882a593Smuzhiyun .platform_data = &jasper_max8649_info,
149*4882a593Smuzhiyun },
150*4882a593Smuzhiyun [1] = {
151*4882a593Smuzhiyun .type = "max8925",
152*4882a593Smuzhiyun .addr = 0x3c,
153*4882a593Smuzhiyun .irq = IRQ_MMP2_PMIC,
154*4882a593Smuzhiyun .platform_data = &jasper_max8925_info,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
159*4882a593Smuzhiyun .clk_delay_cycles = 0x1f,
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
jasper_init(void)162*4882a593Smuzhiyun static void __init jasper_init(void)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /* on-chip devices */
167*4882a593Smuzhiyun mmp2_add_uart(1);
168*4882a593Smuzhiyun mmp2_add_uart(3);
169*4882a593Smuzhiyun mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
170*4882a593Smuzhiyun platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
171*4882a593Smuzhiyun sizeof(struct pxa_gpio_platform_data));
172*4882a593Smuzhiyun platform_device_register(&mmp2_device_gpio);
173*4882a593Smuzhiyun mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun regulator_has_full_constraints();
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
179*4882a593Smuzhiyun .map_io = mmp_map_io,
180*4882a593Smuzhiyun .nr_irqs = JASPER_NR_IRQS,
181*4882a593Smuzhiyun .init_irq = mmp2_init_irq,
182*4882a593Smuzhiyun .init_time = mmp2_timer_init,
183*4882a593Smuzhiyun .init_machine = jasper_init,
184*4882a593Smuzhiyun .restart = mmp_restart,
185*4882a593Smuzhiyun MACHINE_END
186