xref: /OK3568_Linux_fs/kernel/arch/arm/mach-mmp/brownstone.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  linux/arch/arm/mach-mmp/brownstone.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Support for the Marvell Brownstone Development Platform.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *  Copyright (C) 2009-2010 Marvell International Ltd.
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/gpio-pxa.h>
15*4882a593Smuzhiyun #include <linux/gpio/machine.h>
16*4882a593Smuzhiyun #include <linux/regulator/machine.h>
17*4882a593Smuzhiyun #include <linux/regulator/max8649.h>
18*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
19*4882a593Smuzhiyun #include <linux/mfd/max8925.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/mach/arch.h>
23*4882a593Smuzhiyun #include "addr-map.h"
24*4882a593Smuzhiyun #include "mfp-mmp2.h"
25*4882a593Smuzhiyun #include "mmp2.h"
26*4882a593Smuzhiyun #include "irqs.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include "common.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define BROWNSTONE_NR_IRQS	(MMP_NR_IRQS + 40)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define GPIO_5V_ENABLE		(89)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static unsigned long brownstone_pin_config[] __initdata = {
35*4882a593Smuzhiyun 	/* UART1 */
36*4882a593Smuzhiyun 	GPIO29_UART1_RXD,
37*4882a593Smuzhiyun 	GPIO30_UART1_TXD,
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	/* UART3 */
40*4882a593Smuzhiyun 	GPIO51_UART3_RXD,
41*4882a593Smuzhiyun 	GPIO52_UART3_TXD,
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	/* DFI */
44*4882a593Smuzhiyun 	GPIO168_DFI_D0,
45*4882a593Smuzhiyun 	GPIO167_DFI_D1,
46*4882a593Smuzhiyun 	GPIO166_DFI_D2,
47*4882a593Smuzhiyun 	GPIO165_DFI_D3,
48*4882a593Smuzhiyun 	GPIO107_DFI_D4,
49*4882a593Smuzhiyun 	GPIO106_DFI_D5,
50*4882a593Smuzhiyun 	GPIO105_DFI_D6,
51*4882a593Smuzhiyun 	GPIO104_DFI_D7,
52*4882a593Smuzhiyun 	GPIO111_DFI_D8,
53*4882a593Smuzhiyun 	GPIO164_DFI_D9,
54*4882a593Smuzhiyun 	GPIO163_DFI_D10,
55*4882a593Smuzhiyun 	GPIO162_DFI_D11,
56*4882a593Smuzhiyun 	GPIO161_DFI_D12,
57*4882a593Smuzhiyun 	GPIO110_DFI_D13,
58*4882a593Smuzhiyun 	GPIO109_DFI_D14,
59*4882a593Smuzhiyun 	GPIO108_DFI_D15,
60*4882a593Smuzhiyun 	GPIO143_ND_nCS0,
61*4882a593Smuzhiyun 	GPIO144_ND_nCS1,
62*4882a593Smuzhiyun 	GPIO147_ND_nWE,
63*4882a593Smuzhiyun 	GPIO148_ND_nRE,
64*4882a593Smuzhiyun 	GPIO150_ND_ALE,
65*4882a593Smuzhiyun 	GPIO149_ND_CLE,
66*4882a593Smuzhiyun 	GPIO112_ND_RDY0,
67*4882a593Smuzhiyun 	GPIO160_ND_RDY1,
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	/* PMIC */
70*4882a593Smuzhiyun 	PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	/* MMC0 */
73*4882a593Smuzhiyun 	GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
74*4882a593Smuzhiyun 	GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
75*4882a593Smuzhiyun 	GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
76*4882a593Smuzhiyun 	GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
77*4882a593Smuzhiyun 	GPIO136_MMC1_CMD | MFP_PULL_HIGH,
78*4882a593Smuzhiyun 	GPIO139_MMC1_CLK,
79*4882a593Smuzhiyun 	GPIO140_MMC1_CD | MFP_PULL_LOW,
80*4882a593Smuzhiyun 	GPIO141_MMC1_WP | MFP_PULL_LOW,
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	/* MMC1 */
83*4882a593Smuzhiyun 	GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
84*4882a593Smuzhiyun 	GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
85*4882a593Smuzhiyun 	GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
86*4882a593Smuzhiyun 	GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
87*4882a593Smuzhiyun 	GPIO41_MMC2_CMD | MFP_PULL_HIGH,
88*4882a593Smuzhiyun 	GPIO42_MMC2_CLK,
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	/* MMC2 */
91*4882a593Smuzhiyun 	GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
92*4882a593Smuzhiyun 	GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
93*4882a593Smuzhiyun 	GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
94*4882a593Smuzhiyun 	GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
95*4882a593Smuzhiyun 	GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
96*4882a593Smuzhiyun 	GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
97*4882a593Smuzhiyun 	GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
98*4882a593Smuzhiyun 	GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
99*4882a593Smuzhiyun 	GPIO112_MMC3_CMD | MFP_PULL_HIGH,
100*4882a593Smuzhiyun 	GPIO151_MMC3_CLK,
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	/* 5V regulator */
103*4882a593Smuzhiyun 	GPIO89_GPIO,
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
107*4882a593Smuzhiyun 	.irq_base	= MMP_GPIO_TO_IRQ(0),
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static struct regulator_consumer_supply max8649_supply[] = {
111*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vcc_core", NULL),
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun static struct regulator_init_data max8649_init_data = {
115*4882a593Smuzhiyun 	.constraints	= {
116*4882a593Smuzhiyun 		.name		= "vcc_core range",
117*4882a593Smuzhiyun 		.min_uV		= 1150000,
118*4882a593Smuzhiyun 		.max_uV		= 1280000,
119*4882a593Smuzhiyun 		.always_on	= 1,
120*4882a593Smuzhiyun 		.boot_on	= 1,
121*4882a593Smuzhiyun 		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
122*4882a593Smuzhiyun 	},
123*4882a593Smuzhiyun 	.num_consumer_supplies	= 1,
124*4882a593Smuzhiyun 	.consumer_supplies	= &max8649_supply[0],
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun static struct max8649_platform_data brownstone_max8649_info = {
128*4882a593Smuzhiyun 	.mode		= 2,	/* VID1 = 1, VID0 = 0 */
129*4882a593Smuzhiyun 	.extclk		= 0,
130*4882a593Smuzhiyun 	.ramp_timing	= MAX8649_RAMP_32MV,
131*4882a593Smuzhiyun 	.regulator	= &max8649_init_data,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
135*4882a593Smuzhiyun 	REGULATOR_SUPPLY("v_5vp", NULL),
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun static struct regulator_init_data brownstone_v_5vp_data = {
139*4882a593Smuzhiyun 	.constraints	= {
140*4882a593Smuzhiyun 		.valid_ops_mask		= REGULATOR_CHANGE_STATUS,
141*4882a593Smuzhiyun 	},
142*4882a593Smuzhiyun 	.num_consumer_supplies	= ARRAY_SIZE(brownstone_v_5vp_supplies),
143*4882a593Smuzhiyun 	.consumer_supplies	= brownstone_v_5vp_supplies,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static struct fixed_voltage_config brownstone_v_5vp = {
147*4882a593Smuzhiyun 	.supply_name		= "v_5vp",
148*4882a593Smuzhiyun 	.microvolts		= 5000000,
149*4882a593Smuzhiyun 	.enabled_at_boot	= 1,
150*4882a593Smuzhiyun 	.init_data		= &brownstone_v_5vp_data,
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun static struct platform_device brownstone_v_5vp_device = {
154*4882a593Smuzhiyun 	.name		= "reg-fixed-voltage",
155*4882a593Smuzhiyun 	.id		= 1,
156*4882a593Smuzhiyun 	.dev = {
157*4882a593Smuzhiyun 		.platform_data = &brownstone_v_5vp,
158*4882a593Smuzhiyun 	},
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static struct gpiod_lookup_table brownstone_v_5vp_gpiod_table = {
162*4882a593Smuzhiyun 	.dev_id = "reg-fixed-voltage.1", /* .id set to 1 above */
163*4882a593Smuzhiyun 	.table = {
164*4882a593Smuzhiyun 		GPIO_LOOKUP("gpio-pxa", GPIO_5V_ENABLE,
165*4882a593Smuzhiyun 			    NULL, GPIO_ACTIVE_HIGH),
166*4882a593Smuzhiyun 		{ },
167*4882a593Smuzhiyun 	},
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun static struct max8925_platform_data brownstone_max8925_info = {
171*4882a593Smuzhiyun 	.irq_base		= MMP_NR_IRQS,
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun static struct i2c_board_info brownstone_twsi1_info[] = {
175*4882a593Smuzhiyun 	[0] = {
176*4882a593Smuzhiyun 		.type		= "max8649",
177*4882a593Smuzhiyun 		.addr		= 0x60,
178*4882a593Smuzhiyun 		.platform_data	= &brownstone_max8649_info,
179*4882a593Smuzhiyun 	},
180*4882a593Smuzhiyun 	[1] = {
181*4882a593Smuzhiyun 		.type		= "max8925",
182*4882a593Smuzhiyun 		.addr		= 0x3c,
183*4882a593Smuzhiyun 		.irq		= IRQ_MMP2_PMIC,
184*4882a593Smuzhiyun 		.platform_data	= &brownstone_max8925_info,
185*4882a593Smuzhiyun 	},
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
189*4882a593Smuzhiyun 	.clk_delay_cycles = 0x1f,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
193*4882a593Smuzhiyun 	.clk_delay_cycles = 0x1f,
194*4882a593Smuzhiyun 	.flags = PXA_FLAG_CARD_PERMANENT
195*4882a593Smuzhiyun 		| PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun static struct sram_platdata mmp2_asram_platdata = {
199*4882a593Smuzhiyun 	.pool_name	= "asram",
200*4882a593Smuzhiyun 	.granularity	= SRAM_GRANULARITY,
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun static struct sram_platdata mmp2_isram_platdata = {
204*4882a593Smuzhiyun 	.pool_name	= "isram",
205*4882a593Smuzhiyun 	.granularity	= SRAM_GRANULARITY,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
brownstone_init(void)208*4882a593Smuzhiyun static void __init brownstone_init(void)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* on-chip devices */
213*4882a593Smuzhiyun 	mmp2_add_uart(1);
214*4882a593Smuzhiyun 	mmp2_add_uart(3);
215*4882a593Smuzhiyun 	platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
216*4882a593Smuzhiyun 				 sizeof(struct pxa_gpio_platform_data));
217*4882a593Smuzhiyun 	platform_device_register(&mmp2_device_gpio);
218*4882a593Smuzhiyun 	mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
219*4882a593Smuzhiyun 	mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
220*4882a593Smuzhiyun 	mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
221*4882a593Smuzhiyun 	mmp2_add_asram(&mmp2_asram_platdata);
222*4882a593Smuzhiyun 	mmp2_add_isram(&mmp2_isram_platdata);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	/* enable 5v regulator */
225*4882a593Smuzhiyun 	gpiod_add_lookup_table(&brownstone_v_5vp_gpiod_table);
226*4882a593Smuzhiyun 	platform_device_register(&brownstone_v_5vp_device);
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
230*4882a593Smuzhiyun 	/* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
231*4882a593Smuzhiyun 	.map_io		= mmp_map_io,
232*4882a593Smuzhiyun 	.nr_irqs	= BROWNSTONE_NR_IRQS,
233*4882a593Smuzhiyun 	.init_irq	= mmp2_init_irq,
234*4882a593Smuzhiyun 	.init_time	= mmp2_timer_init,
235*4882a593Smuzhiyun 	.init_machine	= brownstone_init,
236*4882a593Smuzhiyun 	.restart	= mmp_restart,
237*4882a593Smuzhiyun MACHINE_END
238