1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Common address map definitions 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ASM_MACH_ADDR_MAP_H 7*4882a593Smuzhiyun #define __ASM_MACH_ADDR_MAP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* APB - Application Subsystem Peripheral Bus 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * NOTE: the DMA controller registers are actually on the AXI fabric #1 12*4882a593Smuzhiyun * slave port to AHB/APB bridge, due to its close relationship to those 13*4882a593Smuzhiyun * peripherals on APB, let's count it into the ABP mapping area. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define APB_PHYS_BASE 0xd4000000 16*4882a593Smuzhiyun #define APB_VIRT_BASE IOMEM(0xfe000000) 17*4882a593Smuzhiyun #define APB_PHYS_SIZE 0x00200000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define AXI_PHYS_BASE 0xd4200000 20*4882a593Smuzhiyun #define AXI_VIRT_BASE IOMEM(0xfe200000) 21*4882a593Smuzhiyun #define AXI_PHYS_SIZE 0x00200000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define PGU_PHYS_BASE 0xe0000000 24*4882a593Smuzhiyun #define PGU_VIRT_BASE IOMEM(0xfe400000) 25*4882a593Smuzhiyun #define PGU_PHYS_SIZE 0x00100000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Static Memory Controller - Chip Select 0 and 1 */ 28*4882a593Smuzhiyun #define SMC_CS0_PHYS_BASE 0x80000000 29*4882a593Smuzhiyun #define SMC_CS0_PHYS_SIZE 0x10000000 30*4882a593Smuzhiyun #define SMC_CS1_PHYS_BASE 0x90000000 31*4882a593Smuzhiyun #define SMC_CS1_PHYS_SIZE 0x10000000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) 34*4882a593Smuzhiyun #define APMU_REG(x) (APMU_VIRT_BASE + (x)) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) 37*4882a593Smuzhiyun #define APBC_REG(x) (APBC_VIRT_BASE + (x)) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) 40*4882a593Smuzhiyun #define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) 43*4882a593Smuzhiyun #define CIU_REG(x) (CIU_VIRT_BASE + (x)) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define SCU_VIRT_BASE (PGU_VIRT_BASE) 46*4882a593Smuzhiyun #define SCU_REG(x) (SCU_VIRT_BASE + (x)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __ASM_MACH_ADDR_MAP_H */ 49