1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Device Tree support for Mediatek SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2014 MundoReader S.L.
6*4882a593Smuzhiyun * Author: Matthias Brugger <matthias.bgg@gmail.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <asm/mach/arch.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_clk.h>
13*4882a593Smuzhiyun #include <linux/clocksource.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define GPT6_CON_MT65xx 0x10008060
17*4882a593Smuzhiyun #define GPT_ENABLE 0x31
18*4882a593Smuzhiyun
mediatek_timer_init(void)19*4882a593Smuzhiyun static void __init mediatek_timer_init(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun void __iomem *gpt_base;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun if (of_machine_is_compatible("mediatek,mt6589") ||
24*4882a593Smuzhiyun of_machine_is_compatible("mediatek,mt7623") ||
25*4882a593Smuzhiyun of_machine_is_compatible("mediatek,mt8135") ||
26*4882a593Smuzhiyun of_machine_is_compatible("mediatek,mt8127")) {
27*4882a593Smuzhiyun /* turn on GPT6 which ungates arch timer clocks */
28*4882a593Smuzhiyun gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* enable clock and set to free-run */
31*4882a593Smuzhiyun writel(GPT_ENABLE, gpt_base);
32*4882a593Smuzhiyun iounmap(gpt_base);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun of_clk_init(NULL);
36*4882a593Smuzhiyun timer_probe();
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const char * const mediatek_board_dt_compat[] = {
40*4882a593Smuzhiyun "mediatek,mt2701",
41*4882a593Smuzhiyun "mediatek,mt6589",
42*4882a593Smuzhiyun "mediatek,mt6592",
43*4882a593Smuzhiyun "mediatek,mt7623",
44*4882a593Smuzhiyun "mediatek,mt7629",
45*4882a593Smuzhiyun "mediatek,mt8127",
46*4882a593Smuzhiyun "mediatek,mt8135",
47*4882a593Smuzhiyun NULL,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
51*4882a593Smuzhiyun .dt_compat = mediatek_board_dt_compat,
52*4882a593Smuzhiyun .init_time = mediatek_timer_init,
53*4882a593Smuzhiyun MACHINE_END
54