1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-lpc32xx/pm.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
5*4882a593Smuzhiyun * Modified by Kevin Wells <kevin.wells@nxp.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * 2005 (c) MontaVista Software, Inc. This file is licensed under
8*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program
9*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express
10*4882a593Smuzhiyun * or implied.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * LPC32XX CPU and system power management
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * The LPC32XX has three CPU modes for controlling system power: run,
17*4882a593Smuzhiyun * direct-run, and halt modes. When switching between halt and run modes,
18*4882a593Smuzhiyun * the CPU transistions through direct-run mode. For Linux, direct-run
19*4882a593Smuzhiyun * mode is not used in normal operation. Halt mode is used when the
20*4882a593Smuzhiyun * system is fully suspended.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Run mode:
23*4882a593Smuzhiyun * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
24*4882a593Smuzhiyun * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
25*4882a593Smuzhiyun * the HCLK_PLL rate. Linux runs in this mode.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * Direct-run mode:
28*4882a593Smuzhiyun * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
29*4882a593Smuzhiyun * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
30*4882a593Smuzhiyun * source or the frequency of the main oscillator. In this mode, the
31*4882a593Smuzhiyun * HCLK_PLL can be safely enabled, changed, or disabled.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * Halt mode:
34*4882a593Smuzhiyun * SYSCLK is gated off and the CPU and system clocks are halted.
35*4882a593Smuzhiyun * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
36*4882a593Smuzhiyun * key scanner, etc.) still operate if enabled. In this state, an enabled
37*4882a593Smuzhiyun * system event (ie, GPIO state change, RTC match, key press, etc.) will
38*4882a593Smuzhiyun * wake the system up back into direct-run mode.
39*4882a593Smuzhiyun *
40*4882a593Smuzhiyun * DRAM refresh
41*4882a593Smuzhiyun * DRAM clocking and refresh are slightly different for systems with DDR
42*4882a593Smuzhiyun * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
43*4882a593Smuzhiyun * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44*4882a593Smuzhiyun * a transition to direct-run mode will stop all DDR accesses (no clocks).
45*4882a593Smuzhiyun * Because of this, the code to switch power modes and the code to enter
46*4882a593Smuzhiyun * and exit DRAM self-refresh modes must not be executed in DRAM. A small
47*4882a593Smuzhiyun * section of IRAM is used instead for this.
48*4882a593Smuzhiyun *
49*4882a593Smuzhiyun * Suspend is handled with the following logic:
50*4882a593Smuzhiyun * Backup a small area of IRAM used for the suspend code
51*4882a593Smuzhiyun * Copy suspend code to IRAM
52*4882a593Smuzhiyun * Transfer control to code in IRAM
53*4882a593Smuzhiyun * Places DRAMs in self-refresh mode
54*4882a593Smuzhiyun * Enter direct-run mode
55*4882a593Smuzhiyun * Save state of HCLK_PLL PLL
56*4882a593Smuzhiyun * Disable HCLK_PLL PLL
57*4882a593Smuzhiyun * Enter halt mode - CPU and buses will stop
58*4882a593Smuzhiyun * System enters direct-run mode when an enabled event occurs
59*4882a593Smuzhiyun * HCLK PLL state is restored
60*4882a593Smuzhiyun * Run mode is entered
61*4882a593Smuzhiyun * DRAMS are placed back into normal mode
62*4882a593Smuzhiyun * Code execution returns from IRAM
63*4882a593Smuzhiyun * IRAM code are used for suspend is restored
64*4882a593Smuzhiyun * Suspend mode is exited
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #include <linux/suspend.h>
68*4882a593Smuzhiyun #include <linux/io.h>
69*4882a593Smuzhiyun #include <linux/slab.h>
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #include <asm/cacheflush.h>
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #include "lpc32xx.h"
74*4882a593Smuzhiyun #include "common.h"
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * Both STANDBY and MEM suspend states are handled the same with no
80*4882a593Smuzhiyun * loss of CPU or memory state
81*4882a593Smuzhiyun */
lpc32xx_pm_enter(suspend_state_t state)82*4882a593Smuzhiyun static int lpc32xx_pm_enter(suspend_state_t state)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun int (*lpc32xx_suspend_ptr) (void);
85*4882a593Smuzhiyun void *iram_swap_area;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Allocate some space for temporary IRAM storage */
88*4882a593Smuzhiyun iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
89*4882a593Smuzhiyun lpc32xx_sys_suspend_sz, GFP_KERNEL);
90*4882a593Smuzhiyun if (!iram_swap_area)
91*4882a593Smuzhiyun return -ENOMEM;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun * Copy code to suspend system into IRAM. The suspend code
95*4882a593Smuzhiyun * needs to run from IRAM as DRAM may no longer be available
96*4882a593Smuzhiyun * when the PLL is stopped.
97*4882a593Smuzhiyun */
98*4882a593Smuzhiyun memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
99*4882a593Smuzhiyun lpc32xx_sys_suspend_sz);
100*4882a593Smuzhiyun flush_icache_range((unsigned long)TEMP_IRAM_AREA,
101*4882a593Smuzhiyun (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Transfer to suspend code in IRAM */
104*4882a593Smuzhiyun lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
105*4882a593Smuzhiyun flush_cache_all();
106*4882a593Smuzhiyun (void) lpc32xx_suspend_ptr();
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* Restore original IRAM contents */
109*4882a593Smuzhiyun memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
110*4882a593Smuzhiyun lpc32xx_sys_suspend_sz);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun kfree(iram_swap_area);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const struct platform_suspend_ops lpc32xx_pm_ops = {
118*4882a593Smuzhiyun .valid = suspend_valid_only_mem,
119*4882a593Smuzhiyun .enter = lpc32xx_pm_enter,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #define EMC_DYN_MEM_CTRL_OFS 0x20
123*4882a593Smuzhiyun #define EMC_SRMMC (1 << 3)
124*4882a593Smuzhiyun #define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
lpc32xx_pm_init(void)125*4882a593Smuzhiyun static int __init lpc32xx_pm_init(void)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun /*
128*4882a593Smuzhiyun * Setup SDRAM self-refresh clock to automatically disable o
129*4882a593Smuzhiyun * start of self-refresh. This only needs to be done once.
130*4882a593Smuzhiyun */
131*4882a593Smuzhiyun __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun suspend_set_ops(&lpc32xx_pm_ops);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun arch_initcall(lpc32xx_pm_init);
138