1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Platform support for LPC32xx SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Kevin Wells <kevin.wells@nxp.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
8*4882a593Smuzhiyun * Copyright (C) 2010 NXP Semiconductors
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/amba/pl08x.h>
12*4882a593Smuzhiyun #include <linux/mtd/lpc32xx_mlc.h>
13*4882a593Smuzhiyun #include <linux/mtd/lpc32xx_slc.h>
14*4882a593Smuzhiyun #include <linux/of_platform.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <asm/mach/arch.h>
17*4882a593Smuzhiyun #include "common.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static struct pl08x_channel_data pl08x_slave_channels[] = {
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun .bus_id = "nand-slc",
22*4882a593Smuzhiyun .min_signal = 1, /* SLC NAND Flash */
23*4882a593Smuzhiyun .max_signal = 1,
24*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
25*4882a593Smuzhiyun },
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun .bus_id = "nand-mlc",
28*4882a593Smuzhiyun .min_signal = 12, /* MLC NAND Flash */
29*4882a593Smuzhiyun .max_signal = 12,
30*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
31*4882a593Smuzhiyun },
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
pl08x_get_signal(const struct pl08x_channel_data * cd)34*4882a593Smuzhiyun static int pl08x_get_signal(const struct pl08x_channel_data *cd)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun return cd->min_signal;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
pl08x_put_signal(const struct pl08x_channel_data * cd,int ch)39*4882a593Smuzhiyun static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static struct pl08x_platform_data pl08x_pd = {
44*4882a593Smuzhiyun /* Some reasonable memcpy defaults */
45*4882a593Smuzhiyun .memcpy_burst_size = PL08X_BURST_SZ_256,
46*4882a593Smuzhiyun .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
47*4882a593Smuzhiyun .slave_channels = &pl08x_slave_channels[0],
48*4882a593Smuzhiyun .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
49*4882a593Smuzhiyun .get_xfer_signal = pl08x_get_signal,
50*4882a593Smuzhiyun .put_xfer_signal = pl08x_put_signal,
51*4882a593Smuzhiyun .lli_buses = PL08X_AHB1,
52*4882a593Smuzhiyun .mem_buses = PL08X_AHB1,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
56*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
60*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
64*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
65*4882a593Smuzhiyun OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
66*4882a593Smuzhiyun &lpc32xx_slc_data),
67*4882a593Smuzhiyun OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
68*4882a593Smuzhiyun &lpc32xx_mlc_data),
69*4882a593Smuzhiyun { }
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
lpc3250_machine_init(void)72*4882a593Smuzhiyun static void __init lpc3250_machine_init(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun lpc32xx_serial_init();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const char *const lpc32xx_dt_compat[] __initconst = {
80*4882a593Smuzhiyun "nxp,lpc3220",
81*4882a593Smuzhiyun "nxp,lpc3230",
82*4882a593Smuzhiyun "nxp,lpc3240",
83*4882a593Smuzhiyun "nxp,lpc3250",
84*4882a593Smuzhiyun NULL
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
88*4882a593Smuzhiyun .atag_offset = 0x100,
89*4882a593Smuzhiyun .map_io = lpc32xx_map_io,
90*4882a593Smuzhiyun .init_machine = lpc3250_machine_init,
91*4882a593Smuzhiyun .dt_compat = lpc32xx_dt_compat,
92*4882a593Smuzhiyun MACHINE_END
93