1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-lpc32xx/common.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Kevin Wells <kevin.wells@nxp.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2010 NXP Semiconductors
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/soc/nxp/lpc32xx-misc.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/mach/map.h>
14*4882a593Smuzhiyun #include <asm/system_info.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "lpc32xx.h"
17*4882a593Smuzhiyun #include "common.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Returns the unique ID for the device
21*4882a593Smuzhiyun */
lpc32xx_get_uid(u32 devid[4])22*4882a593Smuzhiyun void lpc32xx_get_uid(u32 devid[4])
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun int i;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun for (i = 0; i < 4; i++)
27*4882a593Smuzhiyun devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Detects and returns IRAM size for the device variation
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun #define LPC32XX_IRAM_BANK_SIZE SZ_128K
34*4882a593Smuzhiyun static u32 iram_size;
lpc32xx_return_iram(void __iomem ** mapbase,dma_addr_t * dmaaddr)35*4882a593Smuzhiyun u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun if (iram_size == 0) {
38*4882a593Smuzhiyun u32 savedval1, savedval2;
39*4882a593Smuzhiyun void __iomem *iramptr1, *iramptr2;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
42*4882a593Smuzhiyun iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
43*4882a593Smuzhiyun savedval1 = __raw_readl(iramptr1);
44*4882a593Smuzhiyun savedval2 = __raw_readl(iramptr2);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (savedval1 == savedval2) {
47*4882a593Smuzhiyun __raw_writel(savedval2 + 1, iramptr2);
48*4882a593Smuzhiyun if (__raw_readl(iramptr1) == savedval2 + 1)
49*4882a593Smuzhiyun iram_size = LPC32XX_IRAM_BANK_SIZE;
50*4882a593Smuzhiyun else
51*4882a593Smuzhiyun iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
52*4882a593Smuzhiyun __raw_writel(savedval2, iramptr2);
53*4882a593Smuzhiyun } else
54*4882a593Smuzhiyun iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun if (dmaaddr)
57*4882a593Smuzhiyun *dmaaddr = LPC32XX_IRAM_BASE;
58*4882a593Smuzhiyun if (mapbase)
59*4882a593Smuzhiyun *mapbase = io_p2v(LPC32XX_IRAM_BASE);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return iram_size;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
64*4882a593Smuzhiyun
lpc32xx_set_phy_interface_mode(phy_interface_t mode)65*4882a593Smuzhiyun void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
68*4882a593Smuzhiyun tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
69*4882a593Smuzhiyun if (mode == PHY_INTERFACE_MODE_MII)
70*4882a593Smuzhiyun tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
71*4882a593Smuzhiyun else
72*4882a593Smuzhiyun tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
73*4882a593Smuzhiyun __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static struct map_desc lpc32xx_io_desc[] __initdata = {
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
80*4882a593Smuzhiyun .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
81*4882a593Smuzhiyun .length = LPC32XX_AHB0_SIZE,
82*4882a593Smuzhiyun .type = MT_DEVICE
83*4882a593Smuzhiyun },
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
86*4882a593Smuzhiyun .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
87*4882a593Smuzhiyun .length = LPC32XX_AHB1_SIZE,
88*4882a593Smuzhiyun .type = MT_DEVICE
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
92*4882a593Smuzhiyun .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
93*4882a593Smuzhiyun .length = LPC32XX_FABAPB_SIZE,
94*4882a593Smuzhiyun .type = MT_DEVICE
95*4882a593Smuzhiyun },
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
98*4882a593Smuzhiyun .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
99*4882a593Smuzhiyun .length = (LPC32XX_IRAM_BANK_SIZE * 2),
100*4882a593Smuzhiyun .type = MT_DEVICE
101*4882a593Smuzhiyun },
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
lpc32xx_map_io(void)104*4882a593Smuzhiyun void __init lpc32xx_map_io(void)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
lpc32xx_check_uid(void)109*4882a593Smuzhiyun static int __init lpc32xx_check_uid(void)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun u32 uid[4];
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun lpc32xx_get_uid(uid);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
116*4882a593Smuzhiyun uid[3], uid[2], uid[1], uid[0]);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (!system_serial_low && !system_serial_high) {
119*4882a593Smuzhiyun system_serial_low = uid[0];
120*4882a593Smuzhiyun system_serial_high = uid[1];
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return 1;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun arch_initcall(lpc32xx_check_uid);
126