xref: /OK3568_Linux_fs/kernel/arch/arm/mach-ixp4xx/vulcan-setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * arch/arm/mach-ixp4xx/vulcan-setup.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Arcom/Eurotech Vulcan board-setup
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * based on fsg-setup.c:
10*4882a593Smuzhiyun  *	Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/if_ether.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/serial.h>
16*4882a593Smuzhiyun #include <linux/serial_8250.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun #include <linux/w1-gpio.h>
19*4882a593Smuzhiyun #include <linux/gpio/machine.h>
20*4882a593Smuzhiyun #include <linux/mtd/plat-ram.h>
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/mach/arch.h>
23*4882a593Smuzhiyun #include <asm/mach/flash.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include "irqs.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static struct flash_platform_data vulcan_flash_data = {
28*4882a593Smuzhiyun 	.map_name	= "cfi_probe",
29*4882a593Smuzhiyun 	.width		= 2,
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static struct resource vulcan_flash_resource = {
33*4882a593Smuzhiyun 	.flags			= IORESOURCE_MEM,
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun static struct platform_device vulcan_flash = {
37*4882a593Smuzhiyun 	.name			= "IXP4XX-Flash",
38*4882a593Smuzhiyun 	.id			= 0,
39*4882a593Smuzhiyun 	.dev = {
40*4882a593Smuzhiyun 		.platform_data	= &vulcan_flash_data,
41*4882a593Smuzhiyun 	},
42*4882a593Smuzhiyun 	.resource		= &vulcan_flash_resource,
43*4882a593Smuzhiyun 	.num_resources		= 1,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun static struct platdata_mtd_ram vulcan_sram_data = {
47*4882a593Smuzhiyun 	.mapname	= "Vulcan SRAM",
48*4882a593Smuzhiyun 	.bankwidth	= 1,
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun static struct resource vulcan_sram_resource = {
52*4882a593Smuzhiyun 	.flags			= IORESOURCE_MEM,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun static struct platform_device vulcan_sram = {
56*4882a593Smuzhiyun 	.name			= "mtd-ram",
57*4882a593Smuzhiyun 	.id			= 0,
58*4882a593Smuzhiyun 	.dev = {
59*4882a593Smuzhiyun 		.platform_data	= &vulcan_sram_data,
60*4882a593Smuzhiyun 	},
61*4882a593Smuzhiyun 	.resource		= &vulcan_sram_resource,
62*4882a593Smuzhiyun 	.num_resources		= 1,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static struct resource vulcan_uart_resources[] = {
66*4882a593Smuzhiyun 	[0] = {
67*4882a593Smuzhiyun 		.start		= IXP4XX_UART1_BASE_PHYS,
68*4882a593Smuzhiyun 		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
69*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
70*4882a593Smuzhiyun 	},
71*4882a593Smuzhiyun 	[1] = {
72*4882a593Smuzhiyun 		.start		= IXP4XX_UART2_BASE_PHYS,
73*4882a593Smuzhiyun 		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
74*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
75*4882a593Smuzhiyun 	},
76*4882a593Smuzhiyun 	[2] = {
77*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
78*4882a593Smuzhiyun 	},
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun static struct plat_serial8250_port vulcan_uart_data[] = {
82*4882a593Smuzhiyun 	[0] = {
83*4882a593Smuzhiyun 		.mapbase	= IXP4XX_UART1_BASE_PHYS,
84*4882a593Smuzhiyun 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
85*4882a593Smuzhiyun 		.irq		= IRQ_IXP4XX_UART1,
86*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
87*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
88*4882a593Smuzhiyun 		.regshift	= 2,
89*4882a593Smuzhiyun 		.uartclk	= IXP4XX_UART_XTAL,
90*4882a593Smuzhiyun 	},
91*4882a593Smuzhiyun 	[1] = {
92*4882a593Smuzhiyun 		.mapbase	= IXP4XX_UART2_BASE_PHYS,
93*4882a593Smuzhiyun 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
94*4882a593Smuzhiyun 		.irq		= IRQ_IXP4XX_UART2,
95*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
96*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
97*4882a593Smuzhiyun 		.regshift	= 2,
98*4882a593Smuzhiyun 		.uartclk	= IXP4XX_UART_XTAL,
99*4882a593Smuzhiyun 	},
100*4882a593Smuzhiyun 	[2] = {
101*4882a593Smuzhiyun 		.irq		= IXP4XX_GPIO_IRQ(4),
102*4882a593Smuzhiyun 		.irqflags	= IRQF_TRIGGER_LOW,
103*4882a593Smuzhiyun 		.flags		= UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
104*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
105*4882a593Smuzhiyun 		.uartclk	= 1843200,
106*4882a593Smuzhiyun 	},
107*4882a593Smuzhiyun 	[3] = {
108*4882a593Smuzhiyun 		.irq		= IXP4XX_GPIO_IRQ(4),
109*4882a593Smuzhiyun 		.irqflags	= IRQF_TRIGGER_LOW,
110*4882a593Smuzhiyun 		.flags		= UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
111*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
112*4882a593Smuzhiyun 		.uartclk	= 1843200,
113*4882a593Smuzhiyun 	},
114*4882a593Smuzhiyun 	{ }
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun static struct platform_device vulcan_uart = {
118*4882a593Smuzhiyun 	.name			= "serial8250",
119*4882a593Smuzhiyun 	.id			= PLAT8250_DEV_PLATFORM,
120*4882a593Smuzhiyun 	.dev = {
121*4882a593Smuzhiyun 		.platform_data	= vulcan_uart_data,
122*4882a593Smuzhiyun 	},
123*4882a593Smuzhiyun 	.resource		= vulcan_uart_resources,
124*4882a593Smuzhiyun 	.num_resources		= ARRAY_SIZE(vulcan_uart_resources),
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun static struct resource vulcan_npeb_resources[] = {
128*4882a593Smuzhiyun 	{
129*4882a593Smuzhiyun 		.start		= IXP4XX_EthB_BASE_PHYS,
130*4882a593Smuzhiyun 		.end		= IXP4XX_EthB_BASE_PHYS + 0x0fff,
131*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
132*4882a593Smuzhiyun 	},
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun static struct resource vulcan_npec_resources[] = {
136*4882a593Smuzhiyun 	{
137*4882a593Smuzhiyun 		.start		= IXP4XX_EthC_BASE_PHYS,
138*4882a593Smuzhiyun 		.end		= IXP4XX_EthC_BASE_PHYS + 0x0fff,
139*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
140*4882a593Smuzhiyun 	},
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static struct eth_plat_info vulcan_plat_eth[] = {
144*4882a593Smuzhiyun 	[0] = {
145*4882a593Smuzhiyun 		.phy		= 0,
146*4882a593Smuzhiyun 		.rxq		= 3,
147*4882a593Smuzhiyun 		.txreadyq	= 20,
148*4882a593Smuzhiyun 	},
149*4882a593Smuzhiyun 	[1] = {
150*4882a593Smuzhiyun 		.phy		= 1,
151*4882a593Smuzhiyun 		.rxq		= 4,
152*4882a593Smuzhiyun 		.txreadyq	= 21,
153*4882a593Smuzhiyun 	},
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun static struct platform_device vulcan_eth[] = {
157*4882a593Smuzhiyun 	[0] = {
158*4882a593Smuzhiyun 		.name			= "ixp4xx_eth",
159*4882a593Smuzhiyun 		.id			= IXP4XX_ETH_NPEB,
160*4882a593Smuzhiyun 		.dev = {
161*4882a593Smuzhiyun 			.platform_data	= &vulcan_plat_eth[0],
162*4882a593Smuzhiyun 		},
163*4882a593Smuzhiyun 		.num_resources		= ARRAY_SIZE(vulcan_npeb_resources),
164*4882a593Smuzhiyun 		.resource		= vulcan_npeb_resources,
165*4882a593Smuzhiyun 	},
166*4882a593Smuzhiyun 	[1] = {
167*4882a593Smuzhiyun 		.name			= "ixp4xx_eth",
168*4882a593Smuzhiyun 		.id			= IXP4XX_ETH_NPEC,
169*4882a593Smuzhiyun 		.dev = {
170*4882a593Smuzhiyun 			.platform_data	= &vulcan_plat_eth[1],
171*4882a593Smuzhiyun 		},
172*4882a593Smuzhiyun 		.num_resources		= ARRAY_SIZE(vulcan_npec_resources),
173*4882a593Smuzhiyun 		.resource		= vulcan_npec_resources,
174*4882a593Smuzhiyun 	},
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun static struct resource vulcan_max6369_resource = {
178*4882a593Smuzhiyun 	.flags			= IORESOURCE_MEM,
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static struct platform_device vulcan_max6369 = {
182*4882a593Smuzhiyun 	.name			= "max6369_wdt",
183*4882a593Smuzhiyun 	.id			= -1,
184*4882a593Smuzhiyun 	.resource		= &vulcan_max6369_resource,
185*4882a593Smuzhiyun 	.num_resources		= 1,
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun static struct gpiod_lookup_table vulcan_w1_gpiod_table = {
189*4882a593Smuzhiyun 	.dev_id = "w1-gpio",
190*4882a593Smuzhiyun 	.table = {
191*4882a593Smuzhiyun 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", 14, NULL, 0,
192*4882a593Smuzhiyun 				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
193*4882a593Smuzhiyun 	},
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = {
197*4882a593Smuzhiyun 	/* Intentionally left blank */
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static struct platform_device vulcan_w1_gpio = {
201*4882a593Smuzhiyun 	.name			= "w1-gpio",
202*4882a593Smuzhiyun 	.id			= 0,
203*4882a593Smuzhiyun 	.dev			= {
204*4882a593Smuzhiyun 		.platform_data	= &vulcan_w1_gpio_pdata,
205*4882a593Smuzhiyun 	},
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static struct platform_device *vulcan_devices[] __initdata = {
209*4882a593Smuzhiyun 	&vulcan_uart,
210*4882a593Smuzhiyun 	&vulcan_flash,
211*4882a593Smuzhiyun 	&vulcan_sram,
212*4882a593Smuzhiyun 	&vulcan_max6369,
213*4882a593Smuzhiyun 	&vulcan_eth[0],
214*4882a593Smuzhiyun 	&vulcan_eth[1],
215*4882a593Smuzhiyun 	&vulcan_w1_gpio,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun 
vulcan_init(void)218*4882a593Smuzhiyun static void __init vulcan_init(void)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	ixp4xx_sys_init();
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* Flash is spread over both CS0 and CS1 */
223*4882a593Smuzhiyun 	vulcan_flash_resource.start	 = IXP4XX_EXP_BUS_BASE(0);
224*4882a593Smuzhiyun 	vulcan_flash_resource.end	 = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
225*4882a593Smuzhiyun 	*IXP4XX_EXP_CS0 = IXP4XX_EXP_BUS_CS_EN		|
226*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_STROBE_T(3)	|
227*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_SIZE(0xF)	|
228*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_BYTE_RD16	|
229*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_WR_EN;
230*4882a593Smuzhiyun 	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	/* SRAM on CS2, (256kB, 8bit, writable) */
233*4882a593Smuzhiyun 	vulcan_sram_resource.start	= IXP4XX_EXP_BUS_BASE(2);
234*4882a593Smuzhiyun 	vulcan_sram_resource.end	= IXP4XX_EXP_BUS_BASE(2) + SZ_256K - 1;
235*4882a593Smuzhiyun 	*IXP4XX_EXP_CS2 = IXP4XX_EXP_BUS_CS_EN		|
236*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_STROBE_T(1)	|
237*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_HOLD_T(2)	|
238*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_SIZE(9)	|
239*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_SPLT_EN	|
240*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_WR_EN		|
241*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_BYTE_EN;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	/* XR16L2551 on CS3 (Moto style, 512 bytes, 8bits, writable) */
244*4882a593Smuzhiyun 	vulcan_uart_resources[2].start	= IXP4XX_EXP_BUS_BASE(3);
245*4882a593Smuzhiyun 	vulcan_uart_resources[2].end	= IXP4XX_EXP_BUS_BASE(3) + 16 - 1;
246*4882a593Smuzhiyun 	vulcan_uart_data[2].mapbase	= vulcan_uart_resources[2].start;
247*4882a593Smuzhiyun 	vulcan_uart_data[3].mapbase	= vulcan_uart_data[2].mapbase + 8;
248*4882a593Smuzhiyun 	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN		|
249*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_STROBE_T(3)	|
250*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_CYCLES(IXP4XX_EXP_BUS_CYCLES_MOTOROLA)|
251*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_WR_EN		|
252*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_BYTE_EN;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	/* GPIOS on CS4 (512 bytes, 8bits, writable) */
255*4882a593Smuzhiyun 	*IXP4XX_EXP_CS4 = IXP4XX_EXP_BUS_CS_EN		|
256*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_WR_EN		|
257*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_BYTE_EN;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	/* max6369 on CS5 (512 bytes, 8bits, writable) */
260*4882a593Smuzhiyun 	vulcan_max6369_resource.start	= IXP4XX_EXP_BUS_BASE(5);
261*4882a593Smuzhiyun 	vulcan_max6369_resource.end	= IXP4XX_EXP_BUS_BASE(5);
262*4882a593Smuzhiyun 	*IXP4XX_EXP_CS5 = IXP4XX_EXP_BUS_CS_EN		|
263*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_WR_EN		|
264*4882a593Smuzhiyun 			  IXP4XX_EXP_BUS_BYTE_EN;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	gpiod_add_lookup_table(&vulcan_w1_gpiod_table);
267*4882a593Smuzhiyun 	platform_add_devices(vulcan_devices, ARRAY_SIZE(vulcan_devices));
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
271*4882a593Smuzhiyun 	/* Maintainer: Marc Zyngier <maz@misterjones.org> */
272*4882a593Smuzhiyun 	.map_io		= ixp4xx_map_io,
273*4882a593Smuzhiyun 	.init_early	= ixp4xx_init_early,
274*4882a593Smuzhiyun 	.init_irq	= ixp4xx_init_irq,
275*4882a593Smuzhiyun 	.init_time	= ixp4xx_timer_init,
276*4882a593Smuzhiyun 	.atag_offset	= 0x100,
277*4882a593Smuzhiyun 	.init_machine	= vulcan_init,
278*4882a593Smuzhiyun #if defined(CONFIG_PCI)
279*4882a593Smuzhiyun 	.dma_zone_size	= SZ_64M,
280*4882a593Smuzhiyun #endif
281*4882a593Smuzhiyun 	.restart	= ixp4xx_restart,
282*4882a593Smuzhiyun MACHINE_END
283