1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arch/mach-ixp4xx/vulcan-pci.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Vulcan board-level PCI initialization
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * based on ixdp425-pci.c:
10*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation.
11*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <asm/mach/pci.h>
18*4882a593Smuzhiyun #include <asm/mach-types.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "irqs.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* PCI controller GPIO to IRQ pin mappings */
23*4882a593Smuzhiyun #define INTA 2
24*4882a593Smuzhiyun #define INTB 3
25*4882a593Smuzhiyun
vulcan_pci_preinit(void)26*4882a593Smuzhiyun void __init vulcan_pci_preinit(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun #ifndef CONFIG_IXP4XX_INDIRECT_PCI
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Cardbus bridge wants way more than the SoC can actually offer,
31*4882a593Smuzhiyun * and leaves the whole PCI bus in a mess. Artificially limit it
32*4882a593Smuzhiyun * to 8MB per region. Of course indirect mode doesn't have this
33*4882a593Smuzhiyun * limitation...
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun pci_cardbus_mem_size = SZ_8M;
36*4882a593Smuzhiyun pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
37*4882a593Smuzhiyun (int)(pci_cardbus_mem_size >> 20));
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
40*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
41*4882a593Smuzhiyun ixp4xx_pci_preinit();
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
vulcan_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)44*4882a593Smuzhiyun static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun if (slot == 1)
47*4882a593Smuzhiyun return IXP4XX_GPIO_IRQ(INTA);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (slot == 2)
50*4882a593Smuzhiyun return IXP4XX_GPIO_IRQ(INTB);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return -1;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct hw_pci vulcan_pci __initdata = {
56*4882a593Smuzhiyun .nr_controllers = 1,
57*4882a593Smuzhiyun .ops = &ixp4xx_ops,
58*4882a593Smuzhiyun .preinit = vulcan_pci_preinit,
59*4882a593Smuzhiyun .setup = ixp4xx_setup,
60*4882a593Smuzhiyun .map_irq = vulcan_map_irq,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
vulcan_pci_init(void)63*4882a593Smuzhiyun int __init vulcan_pci_init(void)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun if (machine_is_arcom_vulcan())
66*4882a593Smuzhiyun pci_common_init(&vulcan_pci);
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun subsys_initcall(vulcan_pci_init);
71