1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/omixp-setup.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * omicron ixp4xx board setup
6*4882a593Smuzhiyun * Copyright (C) 2009 OMICRON electronics GmbH
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * based nslu2-setup.c, ixdp425-setup.c:
9*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/serial.h>
14*4882a593Smuzhiyun #include <linux/serial_8250.h>
15*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
16*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
17*4882a593Smuzhiyun #include <linux/leds.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <asm/setup.h>
20*4882a593Smuzhiyun #include <asm/memory.h>
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/mach/arch.h>
23*4882a593Smuzhiyun #include <asm/mach/flash.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <mach/hardware.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "irqs.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static struct resource omixp_flash_resources[] = {
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
32*4882a593Smuzhiyun }, {
33*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
34*4882a593Smuzhiyun },
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static struct mtd_partition omixp_partitions[] = {
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun .name = "Recovery Bootloader",
40*4882a593Smuzhiyun .size = 0x00020000,
41*4882a593Smuzhiyun .offset = 0,
42*4882a593Smuzhiyun }, {
43*4882a593Smuzhiyun .name = "Calibration Data",
44*4882a593Smuzhiyun .size = 0x00020000,
45*4882a593Smuzhiyun .offset = 0x00020000,
46*4882a593Smuzhiyun }, {
47*4882a593Smuzhiyun .name = "Recovery FPGA",
48*4882a593Smuzhiyun .size = 0x00020000,
49*4882a593Smuzhiyun .offset = 0x00040000,
50*4882a593Smuzhiyun }, {
51*4882a593Smuzhiyun .name = "Release Bootloader",
52*4882a593Smuzhiyun .size = 0x00020000,
53*4882a593Smuzhiyun .offset = 0x00060000,
54*4882a593Smuzhiyun }, {
55*4882a593Smuzhiyun .name = "Release FPGA",
56*4882a593Smuzhiyun .size = 0x00020000,
57*4882a593Smuzhiyun .offset = 0x00080000,
58*4882a593Smuzhiyun }, {
59*4882a593Smuzhiyun .name = "Kernel",
60*4882a593Smuzhiyun .size = 0x00160000,
61*4882a593Smuzhiyun .offset = 0x000a0000,
62*4882a593Smuzhiyun }, {
63*4882a593Smuzhiyun .name = "Filesystem",
64*4882a593Smuzhiyun .size = 0x00C00000,
65*4882a593Smuzhiyun .offset = 0x00200000,
66*4882a593Smuzhiyun }, {
67*4882a593Smuzhiyun .name = "Persistent Storage",
68*4882a593Smuzhiyun .size = 0x00200000,
69*4882a593Smuzhiyun .offset = 0x00E00000,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static struct flash_platform_data omixp_flash_data[] = {
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun .map_name = "cfi_probe",
76*4882a593Smuzhiyun .parts = omixp_partitions,
77*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(omixp_partitions),
78*4882a593Smuzhiyun }, {
79*4882a593Smuzhiyun .map_name = "cfi_probe",
80*4882a593Smuzhiyun .parts = NULL,
81*4882a593Smuzhiyun .nr_parts = 0,
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static struct platform_device omixp_flash_device[] = {
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun .name = "IXP4XX-Flash",
88*4882a593Smuzhiyun .id = 0,
89*4882a593Smuzhiyun .dev = {
90*4882a593Smuzhiyun .platform_data = &omixp_flash_data[0],
91*4882a593Smuzhiyun },
92*4882a593Smuzhiyun .resource = &omixp_flash_resources[0],
93*4882a593Smuzhiyun .num_resources = 1,
94*4882a593Smuzhiyun }, {
95*4882a593Smuzhiyun .name = "IXP4XX-Flash",
96*4882a593Smuzhiyun .id = 1,
97*4882a593Smuzhiyun .dev = {
98*4882a593Smuzhiyun .platform_data = &omixp_flash_data[1],
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun .resource = &omixp_flash_resources[1],
101*4882a593Smuzhiyun .num_resources = 1,
102*4882a593Smuzhiyun },
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Swap UART's - These boards have the console on UART2. The following
106*4882a593Smuzhiyun * configuration is used:
107*4882a593Smuzhiyun * ttyS0 .. UART2
108*4882a593Smuzhiyun * ttyS1 .. UART1
109*4882a593Smuzhiyun * This way standard images can be used with the kernel that expect
110*4882a593Smuzhiyun * the console on ttyS0.
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun static struct resource omixp_uart_resources[] = {
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun .start = IXP4XX_UART2_BASE_PHYS,
115*4882a593Smuzhiyun .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
116*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
117*4882a593Smuzhiyun }, {
118*4882a593Smuzhiyun .start = IXP4XX_UART1_BASE_PHYS,
119*4882a593Smuzhiyun .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
120*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
121*4882a593Smuzhiyun },
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static struct plat_serial8250_port omixp_uart_data[] = {
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun .mapbase = IXP4XX_UART2_BASE_PHYS,
127*4882a593Smuzhiyun .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
128*4882a593Smuzhiyun .irq = IRQ_IXP4XX_UART2,
129*4882a593Smuzhiyun .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
130*4882a593Smuzhiyun .iotype = UPIO_MEM,
131*4882a593Smuzhiyun .regshift = 2,
132*4882a593Smuzhiyun .uartclk = IXP4XX_UART_XTAL,
133*4882a593Smuzhiyun }, {
134*4882a593Smuzhiyun .mapbase = IXP4XX_UART1_BASE_PHYS,
135*4882a593Smuzhiyun .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
136*4882a593Smuzhiyun .irq = IRQ_IXP4XX_UART1,
137*4882a593Smuzhiyun .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
138*4882a593Smuzhiyun .iotype = UPIO_MEM,
139*4882a593Smuzhiyun .regshift = 2,
140*4882a593Smuzhiyun .uartclk = IXP4XX_UART_XTAL,
141*4882a593Smuzhiyun }, {
142*4882a593Smuzhiyun /* list termination */
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static struct platform_device omixp_uart = {
147*4882a593Smuzhiyun .name = "serial8250",
148*4882a593Smuzhiyun .id = PLAT8250_DEV_PLATFORM,
149*4882a593Smuzhiyun .dev.platform_data = omixp_uart_data,
150*4882a593Smuzhiyun .num_resources = 2,
151*4882a593Smuzhiyun .resource = omixp_uart_resources,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun static struct gpio_led mic256_led_pins[] = {
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun .name = "LED-A",
157*4882a593Smuzhiyun .gpio = 7,
158*4882a593Smuzhiyun },
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun static struct gpio_led_platform_data mic256_led_data = {
162*4882a593Smuzhiyun .num_leds = ARRAY_SIZE(mic256_led_pins),
163*4882a593Smuzhiyun .leds = mic256_led_pins,
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static struct platform_device mic256_leds = {
167*4882a593Smuzhiyun .name = "leds-gpio",
168*4882a593Smuzhiyun .id = -1,
169*4882a593Smuzhiyun .dev.platform_data = &mic256_led_data,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* Built-in 10/100 Ethernet MAC interfaces */
173*4882a593Smuzhiyun static struct resource ixp425_npeb_resources[] = {
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun .start = IXP4XX_EthB_BASE_PHYS,
176*4882a593Smuzhiyun .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
177*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
178*4882a593Smuzhiyun },
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun static struct resource ixp425_npec_resources[] = {
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun .start = IXP4XX_EthC_BASE_PHYS,
184*4882a593Smuzhiyun .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
185*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
186*4882a593Smuzhiyun },
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static struct eth_plat_info ixdp425_plat_eth[] = {
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun .phy = 0,
192*4882a593Smuzhiyun .rxq = 3,
193*4882a593Smuzhiyun .txreadyq = 20,
194*4882a593Smuzhiyun }, {
195*4882a593Smuzhiyun .phy = 1,
196*4882a593Smuzhiyun .rxq = 4,
197*4882a593Smuzhiyun .txreadyq = 21,
198*4882a593Smuzhiyun },
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun static struct platform_device ixdp425_eth[] = {
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun .name = "ixp4xx_eth",
204*4882a593Smuzhiyun .id = IXP4XX_ETH_NPEB,
205*4882a593Smuzhiyun .dev.platform_data = ixdp425_plat_eth,
206*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ixp425_npeb_resources),
207*4882a593Smuzhiyun .resource = ixp425_npeb_resources,
208*4882a593Smuzhiyun }, {
209*4882a593Smuzhiyun .name = "ixp4xx_eth",
210*4882a593Smuzhiyun .id = IXP4XX_ETH_NPEC,
211*4882a593Smuzhiyun .dev.platform_data = ixdp425_plat_eth + 1,
212*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ixp425_npec_resources),
213*4882a593Smuzhiyun .resource = ixp425_npec_resources,
214*4882a593Smuzhiyun },
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun static struct platform_device *devixp_pldev[] __initdata = {
219*4882a593Smuzhiyun &omixp_uart,
220*4882a593Smuzhiyun &omixp_flash_device[0],
221*4882a593Smuzhiyun &ixdp425_eth[0],
222*4882a593Smuzhiyun &ixdp425_eth[1],
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static struct platform_device *mic256_pldev[] __initdata = {
226*4882a593Smuzhiyun &omixp_uart,
227*4882a593Smuzhiyun &omixp_flash_device[0],
228*4882a593Smuzhiyun &mic256_leds,
229*4882a593Smuzhiyun &ixdp425_eth[0],
230*4882a593Smuzhiyun &ixdp425_eth[1],
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun static struct platform_device *miccpt_pldev[] __initdata = {
234*4882a593Smuzhiyun &omixp_uart,
235*4882a593Smuzhiyun &omixp_flash_device[0],
236*4882a593Smuzhiyun &omixp_flash_device[1],
237*4882a593Smuzhiyun &ixdp425_eth[0],
238*4882a593Smuzhiyun &ixdp425_eth[1],
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun
omixp_init(void)241*4882a593Smuzhiyun static void __init omixp_init(void)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun ixp4xx_sys_init();
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* 16MiB Boot Flash */
246*4882a593Smuzhiyun omixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
247*4882a593Smuzhiyun omixp_flash_resources[0].end = IXP4XX_EXP_BUS_END(0);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* 32 MiB Data Flash */
250*4882a593Smuzhiyun omixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
251*4882a593Smuzhiyun omixp_flash_resources[1].end = IXP4XX_EXP_BUS_END(2);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun if (machine_is_devixp())
254*4882a593Smuzhiyun platform_add_devices(devixp_pldev, ARRAY_SIZE(devixp_pldev));
255*4882a593Smuzhiyun else if (machine_is_miccpt())
256*4882a593Smuzhiyun platform_add_devices(miccpt_pldev, ARRAY_SIZE(miccpt_pldev));
257*4882a593Smuzhiyun else if (machine_is_mic256())
258*4882a593Smuzhiyun platform_add_devices(mic256_pldev, ARRAY_SIZE(mic256_pldev));
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun #ifdef CONFIG_MACH_DEVIXP
262*4882a593Smuzhiyun MACHINE_START(DEVIXP, "Omicron DEVIXP")
263*4882a593Smuzhiyun .atag_offset = 0x100,
264*4882a593Smuzhiyun .map_io = ixp4xx_map_io,
265*4882a593Smuzhiyun .init_early = ixp4xx_init_early,
266*4882a593Smuzhiyun .init_irq = ixp4xx_init_irq,
267*4882a593Smuzhiyun .init_time = ixp4xx_timer_init,
268*4882a593Smuzhiyun .init_machine = omixp_init,
269*4882a593Smuzhiyun .restart = ixp4xx_restart,
270*4882a593Smuzhiyun MACHINE_END
271*4882a593Smuzhiyun #endif
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun #ifdef CONFIG_MACH_MICCPT
274*4882a593Smuzhiyun MACHINE_START(MICCPT, "Omicron MICCPT")
275*4882a593Smuzhiyun .atag_offset = 0x100,
276*4882a593Smuzhiyun .map_io = ixp4xx_map_io,
277*4882a593Smuzhiyun .init_early = ixp4xx_init_early,
278*4882a593Smuzhiyun .init_irq = ixp4xx_init_irq,
279*4882a593Smuzhiyun .init_time = ixp4xx_timer_init,
280*4882a593Smuzhiyun .init_machine = omixp_init,
281*4882a593Smuzhiyun #if defined(CONFIG_PCI)
282*4882a593Smuzhiyun .dma_zone_size = SZ_64M,
283*4882a593Smuzhiyun #endif
284*4882a593Smuzhiyun .restart = ixp4xx_restart,
285*4882a593Smuzhiyun MACHINE_END
286*4882a593Smuzhiyun #endif
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun #ifdef CONFIG_MACH_MIC256
289*4882a593Smuzhiyun MACHINE_START(MIC256, "Omicron MIC256")
290*4882a593Smuzhiyun .atag_offset = 0x100,
291*4882a593Smuzhiyun .map_io = ixp4xx_map_io,
292*4882a593Smuzhiyun .init_early = ixp4xx_init_early,
293*4882a593Smuzhiyun .init_irq = ixp4xx_init_irq,
294*4882a593Smuzhiyun .init_time = ixp4xx_timer_init,
295*4882a593Smuzhiyun .init_machine = omixp_init,
296*4882a593Smuzhiyun .restart = ixp4xx_restart,
297*4882a593Smuzhiyun MACHINE_END
298*4882a593Smuzhiyun #endif
299