1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/nas100d-pci.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * NAS 100d board-level PCI initialization
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * based on ixdp425-pci.c:
8*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation.
9*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Maintainer: http://www.nslu2-linux.org/
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <asm/mach/pci.h>
18*4882a593Smuzhiyun #include <asm/mach-types.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "irqs.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define MAX_DEV 3
23*4882a593Smuzhiyun #define IRQ_LINES 3
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* PCI controller GPIO to IRQ pin mappings */
26*4882a593Smuzhiyun #define INTA 11
27*4882a593Smuzhiyun #define INTB 10
28*4882a593Smuzhiyun #define INTC 9
29*4882a593Smuzhiyun #define INTD 8
30*4882a593Smuzhiyun #define INTE 7
31*4882a593Smuzhiyun
nas100d_pci_preinit(void)32*4882a593Smuzhiyun void __init nas100d_pci_preinit(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
35*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
36*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
37*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
38*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
39*4882a593Smuzhiyun ixp4xx_pci_preinit();
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
nas100d_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)42*4882a593Smuzhiyun static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
45*4882a593Smuzhiyun { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
46*4882a593Smuzhiyun { IXP4XX_GPIO_IRQ(INTB), -1, -1 },
47*4882a593Smuzhiyun { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
48*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTE) },
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
52*4882a593Smuzhiyun return pci_irq_table[slot - 1][pin - 1];
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return -1;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct hw_pci __initdata nas100d_pci = {
58*4882a593Smuzhiyun .nr_controllers = 1,
59*4882a593Smuzhiyun .ops = &ixp4xx_ops,
60*4882a593Smuzhiyun .preinit = nas100d_pci_preinit,
61*4882a593Smuzhiyun .setup = ixp4xx_setup,
62*4882a593Smuzhiyun .map_irq = nas100d_map_irq,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
nas100d_pci_init(void)65*4882a593Smuzhiyun int __init nas100d_pci_init(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun if (machine_is_nas100d())
68*4882a593Smuzhiyun pci_common_init(&nas100d_pci);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun subsys_initcall(nas100d_pci_init);
74