1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/miccpt-pci.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * MICCPT board-level PCI initialization
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation.
8*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc.
9*4882a593Smuzhiyun * Copyright (C) 2006 OMICRON electronics GmbH
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Author: Michael Jochum <michael.jochum@omicron.at>
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/irq.h>
19*4882a593Smuzhiyun #include <asm/mach/pci.h>
20*4882a593Smuzhiyun #include <asm/irq.h>
21*4882a593Smuzhiyun #include <mach/hardware.h>
22*4882a593Smuzhiyun #include <asm/mach-types.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "irqs.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define MAX_DEV 4
27*4882a593Smuzhiyun #define IRQ_LINES 4
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* PCI controller GPIO to IRQ pin mappings */
30*4882a593Smuzhiyun #define INTA 1
31*4882a593Smuzhiyun #define INTB 2
32*4882a593Smuzhiyun #define INTC 3
33*4882a593Smuzhiyun #define INTD 4
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun
miccpt_pci_preinit(void)36*4882a593Smuzhiyun void __init miccpt_pci_preinit(void)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
39*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
40*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
41*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
42*4882a593Smuzhiyun ixp4xx_pci_preinit();
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
miccpt_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)45*4882a593Smuzhiyun static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun static int pci_irq_table[IRQ_LINES] = {
48*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTA),
49*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTB),
50*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTC),
51*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTD)
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
55*4882a593Smuzhiyun return pci_irq_table[(slot + pin - 2) % 4];
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return -1;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun struct hw_pci miccpt_pci __initdata = {
61*4882a593Smuzhiyun .nr_controllers = 1,
62*4882a593Smuzhiyun .ops = &ixp4xx_ops,
63*4882a593Smuzhiyun .preinit = miccpt_pci_preinit,
64*4882a593Smuzhiyun .setup = ixp4xx_setup,
65*4882a593Smuzhiyun .map_irq = miccpt_map_irq,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
miccpt_pci_init(void)68*4882a593Smuzhiyun int __init miccpt_pci_init(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun if (machine_is_miccpt())
71*4882a593Smuzhiyun pci_common_init(&miccpt_pci);
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun subsys_initcall(miccpt_pci_init);
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