1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/include/mach/irqs.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * IRQ definitions for IXP4XX based systems 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation. 8*4882a593Smuzhiyun * Copyright (C) 2003 MontaVista Software, Inc. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _ARCH_IXP4XX_IRQS_H_ 12*4882a593Smuzhiyun #define _ARCH_IXP4XX_IRQS_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define IRQ_IXP4XX_BASE 16 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define IRQ_IXP4XX_NPEA (IRQ_IXP4XX_BASE + 0) 17*4882a593Smuzhiyun #define IRQ_IXP4XX_NPEB (IRQ_IXP4XX_BASE + 1) 18*4882a593Smuzhiyun #define IRQ_IXP4XX_NPEC (IRQ_IXP4XX_BASE + 2) 19*4882a593Smuzhiyun #define IRQ_IXP4XX_QM1 (IRQ_IXP4XX_BASE + 3) 20*4882a593Smuzhiyun #define IRQ_IXP4XX_QM2 (IRQ_IXP4XX_BASE + 4) 21*4882a593Smuzhiyun #define IRQ_IXP4XX_TIMER1 (IRQ_IXP4XX_BASE + 5) 22*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO0 (IRQ_IXP4XX_BASE + 6) 23*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO1 (IRQ_IXP4XX_BASE + 7) 24*4882a593Smuzhiyun #define IRQ_IXP4XX_PCI_INT (IRQ_IXP4XX_BASE + 8) 25*4882a593Smuzhiyun #define IRQ_IXP4XX_PCI_DMA1 (IRQ_IXP4XX_BASE + 9) 26*4882a593Smuzhiyun #define IRQ_IXP4XX_PCI_DMA2 (IRQ_IXP4XX_BASE + 10) 27*4882a593Smuzhiyun #define IRQ_IXP4XX_TIMER2 (IRQ_IXP4XX_BASE + 11) 28*4882a593Smuzhiyun #define IRQ_IXP4XX_USB (IRQ_IXP4XX_BASE + 12) 29*4882a593Smuzhiyun #define IRQ_IXP4XX_UART2 (IRQ_IXP4XX_BASE + 13) 30*4882a593Smuzhiyun #define IRQ_IXP4XX_TIMESTAMP (IRQ_IXP4XX_BASE + 14) 31*4882a593Smuzhiyun #define IRQ_IXP4XX_UART1 (IRQ_IXP4XX_BASE + 15) 32*4882a593Smuzhiyun #define IRQ_IXP4XX_WDOG (IRQ_IXP4XX_BASE + 16) 33*4882a593Smuzhiyun #define IRQ_IXP4XX_AHB_PMU (IRQ_IXP4XX_BASE + 17) 34*4882a593Smuzhiyun #define IRQ_IXP4XX_XSCALE_PMU (IRQ_IXP4XX_BASE + 18) 35*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO2 (IRQ_IXP4XX_BASE + 19) 36*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO3 (IRQ_IXP4XX_BASE + 20) 37*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO4 (IRQ_IXP4XX_BASE + 21) 38*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO5 (IRQ_IXP4XX_BASE + 22) 39*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO6 (IRQ_IXP4XX_BASE + 23) 40*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO7 (IRQ_IXP4XX_BASE + 24) 41*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO8 (IRQ_IXP4XX_BASE + 25) 42*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO9 (IRQ_IXP4XX_BASE + 26) 43*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO10 (IRQ_IXP4XX_BASE + 27) 44*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO11 (IRQ_IXP4XX_BASE + 28) 45*4882a593Smuzhiyun #define IRQ_IXP4XX_GPIO12 (IRQ_IXP4XX_BASE + 29) 46*4882a593Smuzhiyun #define IRQ_IXP4XX_SW_INT1 (IRQ_IXP4XX_BASE + 30) 47*4882a593Smuzhiyun #define IRQ_IXP4XX_SW_INT2 (IRQ_IXP4XX_BASE + 31) 48*4882a593Smuzhiyun #define IRQ_IXP4XX_USB_HOST (IRQ_IXP4XX_BASE + 32) 49*4882a593Smuzhiyun #define IRQ_IXP4XX_I2C (IRQ_IXP4XX_BASE + 33) 50*4882a593Smuzhiyun #define IRQ_IXP4XX_SSP (IRQ_IXP4XX_BASE + 34) 51*4882a593Smuzhiyun #define IRQ_IXP4XX_TSYNC (IRQ_IXP4XX_BASE + 35) 52*4882a593Smuzhiyun #define IRQ_IXP4XX_EAU_DONE (IRQ_IXP4XX_BASE + 36) 53*4882a593Smuzhiyun #define IRQ_IXP4XX_SHA_DONE (IRQ_IXP4XX_BASE + 37) 54*4882a593Smuzhiyun #define IRQ_IXP4XX_SWCP_PE (IRQ_IXP4XX_BASE + 58) 55*4882a593Smuzhiyun #define IRQ_IXP4XX_QM_PE (IRQ_IXP4XX_BASE + 60) 56*4882a593Smuzhiyun #define IRQ_IXP4XX_MCU_ECC (IRQ_IXP4XX_BASE + 61) 57*4882a593Smuzhiyun #define IRQ_IXP4XX_EXP_PE (IRQ_IXP4XX_BASE + 62) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n) 60*4882a593Smuzhiyun #define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif 65