1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Register definitions for IXP4xx chipset. This file contains 6*4882a593Smuzhiyun * register location and bit definitions only. Platform specific 7*4882a593Smuzhiyun * definitions and helper function declarations are in platform.h 8*4882a593Smuzhiyun * and machine-name.h. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation. 11*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _ASM_ARM_IXP4XX_H_ 15*4882a593Smuzhiyun #define _ASM_ARM_IXP4XX_H_ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * IXP4xx Linux Memory Map: 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * Phy Size Virt Description 21*4882a593Smuzhiyun * ========================================================================= 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * 0x48000000 0x04000000 ioremap'd PCI Memory Space 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * 0x50000000 0x10000000 ioremap'd EXP BUS 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * 0xC0000000 0x00001000 0xFEF13000 PCI CFG 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * 0xC4000000 0x00001000 0xFEF14000 EXP CFG 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * 0x60000000 0x00004000 0xFEF15000 QMgr 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Queue Manager 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define IXP4XX_QMGR_BASE_PHYS 0x60000000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * Peripheral space, including debug UART. Must be section-aligned so that 45*4882a593Smuzhiyun * it can be used with the low-level debug code. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 48*4882a593Smuzhiyun #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) 49*4882a593Smuzhiyun #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * PCI Config registers 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 55*4882a593Smuzhiyun #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) 56*4882a593Smuzhiyun #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Expansion BUS Configuration registers 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 62*4882a593Smuzhiyun #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 63*4882a593Smuzhiyun #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define IXP4XX_EXP_CS0_OFFSET 0x00 66*4882a593Smuzhiyun #define IXP4XX_EXP_CS1_OFFSET 0x04 67*4882a593Smuzhiyun #define IXP4XX_EXP_CS2_OFFSET 0x08 68*4882a593Smuzhiyun #define IXP4XX_EXP_CS3_OFFSET 0x0C 69*4882a593Smuzhiyun #define IXP4XX_EXP_CS4_OFFSET 0x10 70*4882a593Smuzhiyun #define IXP4XX_EXP_CS5_OFFSET 0x14 71*4882a593Smuzhiyun #define IXP4XX_EXP_CS6_OFFSET 0x18 72*4882a593Smuzhiyun #define IXP4XX_EXP_CS7_OFFSET 0x1C 73*4882a593Smuzhiyun #define IXP4XX_EXP_CFG0_OFFSET 0x20 74*4882a593Smuzhiyun #define IXP4XX_EXP_CFG1_OFFSET 0x24 75*4882a593Smuzhiyun #define IXP4XX_EXP_CFG2_OFFSET 0x28 76*4882a593Smuzhiyun #define IXP4XX_EXP_CFG3_OFFSET 0x2C 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * Expansion Bus Controller registers. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) 84*4882a593Smuzhiyun #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) 85*4882a593Smuzhiyun #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 86*4882a593Smuzhiyun #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) 87*4882a593Smuzhiyun #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) 88*4882a593Smuzhiyun #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) 89*4882a593Smuzhiyun #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) 90*4882a593Smuzhiyun #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 93*4882a593Smuzhiyun #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 94*4882a593Smuzhiyun #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 95*4882a593Smuzhiyun #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* 99*4882a593Smuzhiyun * Peripheral Space Register Region Base Addresses 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) 102*4882a593Smuzhiyun #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) 103*4882a593Smuzhiyun #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) 104*4882a593Smuzhiyun #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) 105*4882a593Smuzhiyun #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) 106*4882a593Smuzhiyun #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) 107*4882a593Smuzhiyun #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) 108*4882a593Smuzhiyun #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) 109*4882a593Smuzhiyun #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) 110*4882a593Smuzhiyun #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) 111*4882a593Smuzhiyun #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) 112*4882a593Smuzhiyun #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) 113*4882a593Smuzhiyun /* ixp46X only */ 114*4882a593Smuzhiyun #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) 115*4882a593Smuzhiyun #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) 116*4882a593Smuzhiyun #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) 117*4882a593Smuzhiyun #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) 118*4882a593Smuzhiyun #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) 119*4882a593Smuzhiyun #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) 120*4882a593Smuzhiyun #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) 124*4882a593Smuzhiyun #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) 125*4882a593Smuzhiyun #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) 126*4882a593Smuzhiyun #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) 127*4882a593Smuzhiyun #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) 128*4882a593Smuzhiyun #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) 129*4882a593Smuzhiyun #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) 130*4882a593Smuzhiyun #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) 131*4882a593Smuzhiyun #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) 132*4882a593Smuzhiyun /* ixp46X only */ 133*4882a593Smuzhiyun #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) 134*4882a593Smuzhiyun #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) 135*4882a593Smuzhiyun #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) 136*4882a593Smuzhiyun #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) 137*4882a593Smuzhiyun #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) 138*4882a593Smuzhiyun #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) 139*4882a593Smuzhiyun #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* 142*4882a593Smuzhiyun * Constants to make it easy to access Timer Control/Status registers 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ 145*4882a593Smuzhiyun #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ 146*4882a593Smuzhiyun #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ 147*4882a593Smuzhiyun #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ 148*4882a593Smuzhiyun #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ 149*4882a593Smuzhiyun #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ 150*4882a593Smuzhiyun #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ 151*4882a593Smuzhiyun #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ 152*4882a593Smuzhiyun #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * Operating System Timer Register Definitions. 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) 161*4882a593Smuzhiyun #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) 162*4882a593Smuzhiyun #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) 163*4882a593Smuzhiyun #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) 164*4882a593Smuzhiyun #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) 165*4882a593Smuzhiyun #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) 166*4882a593Smuzhiyun #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) 167*4882a593Smuzhiyun #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) 168*4882a593Smuzhiyun #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * Timer register values and bit definitions 172*4882a593Smuzhiyun */ 173*4882a593Smuzhiyun #define IXP4XX_OST_ENABLE 0x00000001 174*4882a593Smuzhiyun #define IXP4XX_OST_ONE_SHOT 0x00000002 175*4882a593Smuzhiyun /* Low order bits of reload value ignored */ 176*4882a593Smuzhiyun #define IXP4XX_OST_RELOAD_MASK 0x00000003 177*4882a593Smuzhiyun #define IXP4XX_OST_DISABLED 0x00000000 178*4882a593Smuzhiyun #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 179*4882a593Smuzhiyun #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 180*4882a593Smuzhiyun #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 181*4882a593Smuzhiyun #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 182*4882a593Smuzhiyun #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define IXP4XX_WDT_KEY 0x0000482E 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define IXP4XX_WDT_RESET_ENABLE 0x00000001 187*4882a593Smuzhiyun #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 188*4882a593Smuzhiyun #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* 192*4882a593Smuzhiyun * Constants to make it easy to access PCI Control/Status registers 193*4882a593Smuzhiyun */ 194*4882a593Smuzhiyun #define PCI_NP_AD_OFFSET 0x00 195*4882a593Smuzhiyun #define PCI_NP_CBE_OFFSET 0x04 196*4882a593Smuzhiyun #define PCI_NP_WDATA_OFFSET 0x08 197*4882a593Smuzhiyun #define PCI_NP_RDATA_OFFSET 0x0c 198*4882a593Smuzhiyun #define PCI_CRP_AD_CBE_OFFSET 0x10 199*4882a593Smuzhiyun #define PCI_CRP_WDATA_OFFSET 0x14 200*4882a593Smuzhiyun #define PCI_CRP_RDATA_OFFSET 0x18 201*4882a593Smuzhiyun #define PCI_CSR_OFFSET 0x1c 202*4882a593Smuzhiyun #define PCI_ISR_OFFSET 0x20 203*4882a593Smuzhiyun #define PCI_INTEN_OFFSET 0x24 204*4882a593Smuzhiyun #define PCI_DMACTRL_OFFSET 0x28 205*4882a593Smuzhiyun #define PCI_AHBMEMBASE_OFFSET 0x2c 206*4882a593Smuzhiyun #define PCI_AHBIOBASE_OFFSET 0x30 207*4882a593Smuzhiyun #define PCI_PCIMEMBASE_OFFSET 0x34 208*4882a593Smuzhiyun #define PCI_AHBDOORBELL_OFFSET 0x38 209*4882a593Smuzhiyun #define PCI_PCIDOORBELL_OFFSET 0x3C 210*4882a593Smuzhiyun #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 211*4882a593Smuzhiyun #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 212*4882a593Smuzhiyun #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 213*4882a593Smuzhiyun #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C 214*4882a593Smuzhiyun #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 215*4882a593Smuzhiyun #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* 218*4882a593Smuzhiyun * PCI Control/Status Registers 219*4882a593Smuzhiyun */ 220*4882a593Smuzhiyun #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) 223*4882a593Smuzhiyun #define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) 224*4882a593Smuzhiyun #define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) 225*4882a593Smuzhiyun #define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) 226*4882a593Smuzhiyun #define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) 227*4882a593Smuzhiyun #define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) 228*4882a593Smuzhiyun #define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) 229*4882a593Smuzhiyun #define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 230*4882a593Smuzhiyun #define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET) 231*4882a593Smuzhiyun #define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) 232*4882a593Smuzhiyun #define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) 233*4882a593Smuzhiyun #define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) 234*4882a593Smuzhiyun #define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) 235*4882a593Smuzhiyun #define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) 236*4882a593Smuzhiyun #define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) 237*4882a593Smuzhiyun #define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) 238*4882a593Smuzhiyun #define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) 239*4882a593Smuzhiyun #define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) 240*4882a593Smuzhiyun #define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) 241*4882a593Smuzhiyun #define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) 242*4882a593Smuzhiyun #define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) 243*4882a593Smuzhiyun #define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* 246*4882a593Smuzhiyun * PCI register values and bit definitions 247*4882a593Smuzhiyun */ 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* CSR bit definitions */ 250*4882a593Smuzhiyun #define PCI_CSR_HOST 0x00000001 251*4882a593Smuzhiyun #define PCI_CSR_ARBEN 0x00000002 252*4882a593Smuzhiyun #define PCI_CSR_ADS 0x00000004 253*4882a593Smuzhiyun #define PCI_CSR_PDS 0x00000008 254*4882a593Smuzhiyun #define PCI_CSR_ABE 0x00000010 255*4882a593Smuzhiyun #define PCI_CSR_DBT 0x00000020 256*4882a593Smuzhiyun #define PCI_CSR_ASE 0x00000100 257*4882a593Smuzhiyun #define PCI_CSR_IC 0x00008000 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* ISR (Interrupt status) Register bit definitions */ 260*4882a593Smuzhiyun #define PCI_ISR_PSE 0x00000001 261*4882a593Smuzhiyun #define PCI_ISR_PFE 0x00000002 262*4882a593Smuzhiyun #define PCI_ISR_PPE 0x00000004 263*4882a593Smuzhiyun #define PCI_ISR_AHBE 0x00000008 264*4882a593Smuzhiyun #define PCI_ISR_APDC 0x00000010 265*4882a593Smuzhiyun #define PCI_ISR_PADC 0x00000020 266*4882a593Smuzhiyun #define PCI_ISR_ADB 0x00000040 267*4882a593Smuzhiyun #define PCI_ISR_PDB 0x00000080 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* INTEN (Interrupt Enable) Register bit definitions */ 270*4882a593Smuzhiyun #define PCI_INTEN_PSE 0x00000001 271*4882a593Smuzhiyun #define PCI_INTEN_PFE 0x00000002 272*4882a593Smuzhiyun #define PCI_INTEN_PPE 0x00000004 273*4882a593Smuzhiyun #define PCI_INTEN_AHBE 0x00000008 274*4882a593Smuzhiyun #define PCI_INTEN_APDC 0x00000010 275*4882a593Smuzhiyun #define PCI_INTEN_PADC 0x00000020 276*4882a593Smuzhiyun #define PCI_INTEN_ADB 0x00000040 277*4882a593Smuzhiyun #define PCI_INTEN_PDB 0x00000080 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun /* 280*4882a593Smuzhiyun * Shift value for byte enable on NP cmd/byte enable register 281*4882a593Smuzhiyun */ 282*4882a593Smuzhiyun #define IXP4XX_PCI_NP_CBE_BESL 4 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun /* 285*4882a593Smuzhiyun * PCI commands supported by NP access unit 286*4882a593Smuzhiyun */ 287*4882a593Smuzhiyun #define NP_CMD_IOREAD 0x2 288*4882a593Smuzhiyun #define NP_CMD_IOWRITE 0x3 289*4882a593Smuzhiyun #define NP_CMD_CONFIGREAD 0xa 290*4882a593Smuzhiyun #define NP_CMD_CONFIGWRITE 0xb 291*4882a593Smuzhiyun #define NP_CMD_MEMREAD 0x6 292*4882a593Smuzhiyun #define NP_CMD_MEMWRITE 0x7 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* 295*4882a593Smuzhiyun * Constants for CRP access into local config space 296*4882a593Smuzhiyun */ 297*4882a593Smuzhiyun #define CRP_AD_CBE_BESL 20 298*4882a593Smuzhiyun #define CRP_AD_CBE_WRITE 0x00010000 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun /* "fuse" bits of IXP_EXP_CFG2 */ 303*4882a593Smuzhiyun /* All IXP4xx CPUs */ 304*4882a593Smuzhiyun #define IXP4XX_FEATURE_RCOMP (1 << 0) 305*4882a593Smuzhiyun #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) 306*4882a593Smuzhiyun #define IXP4XX_FEATURE_HASH (1 << 2) 307*4882a593Smuzhiyun #define IXP4XX_FEATURE_AES (1 << 3) 308*4882a593Smuzhiyun #define IXP4XX_FEATURE_DES (1 << 4) 309*4882a593Smuzhiyun #define IXP4XX_FEATURE_HDLC (1 << 5) 310*4882a593Smuzhiyun #define IXP4XX_FEATURE_AAL (1 << 6) 311*4882a593Smuzhiyun #define IXP4XX_FEATURE_HSS (1 << 7) 312*4882a593Smuzhiyun #define IXP4XX_FEATURE_UTOPIA (1 << 8) 313*4882a593Smuzhiyun #define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) 314*4882a593Smuzhiyun #define IXP4XX_FEATURE_NPEC_ETH (1 << 10) 315*4882a593Smuzhiyun #define IXP4XX_FEATURE_RESET_NPEA (1 << 11) 316*4882a593Smuzhiyun #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) 317*4882a593Smuzhiyun #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) 318*4882a593Smuzhiyun #define IXP4XX_FEATURE_PCI (1 << 14) 319*4882a593Smuzhiyun #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) 320*4882a593Smuzhiyun #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) 321*4882a593Smuzhiyun #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ 322*4882a593Smuzhiyun IXP4XX_FEATURE_USB_DEVICE | \ 323*4882a593Smuzhiyun IXP4XX_FEATURE_HASH | \ 324*4882a593Smuzhiyun IXP4XX_FEATURE_AES | \ 325*4882a593Smuzhiyun IXP4XX_FEATURE_DES | \ 326*4882a593Smuzhiyun IXP4XX_FEATURE_HDLC | \ 327*4882a593Smuzhiyun IXP4XX_FEATURE_AAL | \ 328*4882a593Smuzhiyun IXP4XX_FEATURE_HSS | \ 329*4882a593Smuzhiyun IXP4XX_FEATURE_UTOPIA | \ 330*4882a593Smuzhiyun IXP4XX_FEATURE_NPEB_ETH0 | \ 331*4882a593Smuzhiyun IXP4XX_FEATURE_NPEC_ETH | \ 332*4882a593Smuzhiyun IXP4XX_FEATURE_RESET_NPEA | \ 333*4882a593Smuzhiyun IXP4XX_FEATURE_RESET_NPEB | \ 334*4882a593Smuzhiyun IXP4XX_FEATURE_RESET_NPEC | \ 335*4882a593Smuzhiyun IXP4XX_FEATURE_PCI | \ 336*4882a593Smuzhiyun IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ 337*4882a593Smuzhiyun IXP4XX_FEATURE_XSCALE_MAX_FREQ) 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* IXP43x/46x CPUs */ 341*4882a593Smuzhiyun #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) 342*4882a593Smuzhiyun #define IXP4XX_FEATURE_USB_HOST (1 << 18) 343*4882a593Smuzhiyun #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) 344*4882a593Smuzhiyun #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ 345*4882a593Smuzhiyun IXP4XX_FEATURE_ECC_TIMESYNC | \ 346*4882a593Smuzhiyun IXP4XX_FEATURE_USB_HOST | \ 347*4882a593Smuzhiyun IXP4XX_FEATURE_NPEA_ETH) 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun /* IXP46x CPU (including IXP455) only */ 350*4882a593Smuzhiyun #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) 351*4882a593Smuzhiyun #define IXP4XX_FEATURE_RSA (1 << 21) 352*4882a593Smuzhiyun #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ 353*4882a593Smuzhiyun IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ 354*4882a593Smuzhiyun IXP4XX_FEATURE_RSA) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #endif 357