1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/include/mach/cpu.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * IXP4XX cpu type detection 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2007 MontaVista Software, Inc. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_CPU_H__ 11*4882a593Smuzhiyun #define __ASM_ARCH_CPU_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/io.h> 14*4882a593Smuzhiyun #include <asm/cputype.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Processor id value in CP15 Register 0 */ 17*4882a593Smuzhiyun #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */ 18*4882a593Smuzhiyun #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define IXP43X_PROCESSOR_ID_VALUE 0x69054040 21*4882a593Smuzhiyun #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ 24*4882a593Smuzhiyun #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \ 27*4882a593Smuzhiyun IXP42X_PROCESSOR_ID_VALUE) 28*4882a593Smuzhiyun #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ 29*4882a593Smuzhiyun IXP42X_PROCESSOR_ID_VALUE) 30*4882a593Smuzhiyun #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ 31*4882a593Smuzhiyun IXP43X_PROCESSOR_ID_VALUE) 32*4882a593Smuzhiyun #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ 33*4882a593Smuzhiyun IXP46X_PROCESSOR_ID_VALUE) 34*4882a593Smuzhiyun ixp4xx_read_feature_bits(void)35*4882a593Smuzhiyunstatic inline u32 ixp4xx_read_feature_bits(void) 36*4882a593Smuzhiyun { 37*4882a593Smuzhiyun u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun if (cpu_is_ixp42x_rev_a0()) 40*4882a593Smuzhiyun return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | 41*4882a593Smuzhiyun IXP4XX_FEATURE_AES); 42*4882a593Smuzhiyun if (cpu_is_ixp42x()) 43*4882a593Smuzhiyun return val & IXP42X_FEATURE_MASK; 44*4882a593Smuzhiyun if (cpu_is_ixp43x()) 45*4882a593Smuzhiyun return val & IXP43X_FEATURE_MASK; 46*4882a593Smuzhiyun return val & IXP46X_FEATURE_MASK; 47*4882a593Smuzhiyun } 48*4882a593Smuzhiyun ixp4xx_write_feature_bits(u32 value)49*4882a593Smuzhiyunstatic inline void ixp4xx_write_feature_bits(u32 value) 50*4882a593Smuzhiyun { 51*4882a593Smuzhiyun __raw_writel(~value, IXP4XX_EXP_CFG2); 52*4882a593Smuzhiyun } 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* _ASM_ARCH_CPU_H */ 55