1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/gtwx5715-setup.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Gemtek GTWX5715 (Linksys WRV54G) board setup
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2004 George T. Joseph
8*4882a593Smuzhiyun * Derived from Coyote
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/serial.h>
14*4882a593Smuzhiyun #include <linux/tty.h>
15*4882a593Smuzhiyun #include <linux/serial_8250.h>
16*4882a593Smuzhiyun #include <asm/types.h>
17*4882a593Smuzhiyun #include <asm/setup.h>
18*4882a593Smuzhiyun #include <asm/memory.h>
19*4882a593Smuzhiyun #include <mach/hardware.h>
20*4882a593Smuzhiyun #include <asm/irq.h>
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/mach/arch.h>
23*4882a593Smuzhiyun #include <asm/mach/flash.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "irqs.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch
28*4882a593Smuzhiyun and operate as an SPI type interface. The details of the interface
29*4882a593Smuzhiyun are available on Kendin/Micrel's web site. */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define GTWX5715_KSSPI_SELECT 5
32*4882a593Smuzhiyun #define GTWX5715_KSSPI_TXD 6
33*4882a593Smuzhiyun #define GTWX5715_KSSPI_CLOCK 7
34*4882a593Smuzhiyun #define GTWX5715_KSSPI_RXD 12
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* The "reset" button is wired to GPIO 3.
37*4882a593Smuzhiyun The GPIO is brought "low" when the button is pushed. */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define GTWX5715_BUTTON_GPIO 3
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Board Label Front Label
42*4882a593Smuzhiyun LED1 Power
43*4882a593Smuzhiyun LED2 Wireless-G
44*4882a593Smuzhiyun LED3 not populated but could be
45*4882a593Smuzhiyun LED4 Internet
46*4882a593Smuzhiyun LED5 - LED8 Controlled by KS8995M Switch
47*4882a593Smuzhiyun LED9 DMZ */
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define GTWX5715_LED1_GPIO 2
50*4882a593Smuzhiyun #define GTWX5715_LED2_GPIO 9
51*4882a593Smuzhiyun #define GTWX5715_LED3_GPIO 8
52*4882a593Smuzhiyun #define GTWX5715_LED4_GPIO 1
53*4882a593Smuzhiyun #define GTWX5715_LED9_GPIO 4
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Xscale UART registers are 32 bits wide with only the least
57*4882a593Smuzhiyun * significant 8 bits having any meaning. From a configuration
58*4882a593Smuzhiyun * perspective, this means 2 things...
59*4882a593Smuzhiyun *
60*4882a593Smuzhiyun * Setting .regshift = 2 so that the standard 16550 registers
61*4882a593Smuzhiyun * line up on every 4th byte.
62*4882a593Smuzhiyun *
63*4882a593Smuzhiyun * Shifting the register start virtual address +3 bytes when
64*4882a593Smuzhiyun * compiled big-endian. Since register writes are done on a
65*4882a593Smuzhiyun * single byte basis, if the shift isn't done the driver will
66*4882a593Smuzhiyun * write the value into the most significant byte of the register,
67*4882a593Smuzhiyun * which is ignored, instead of the least significant.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #ifdef __ARMEB__
71*4882a593Smuzhiyun #define REG_OFFSET 3
72*4882a593Smuzhiyun #else
73*4882a593Smuzhiyun #define REG_OFFSET 0
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * Only the second or "console" uart is connected on the gtwx5715.
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static struct resource gtwx5715_uart_resources[] = {
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun .start = IXP4XX_UART2_BASE_PHYS,
83*4882a593Smuzhiyun .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
84*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
85*4882a593Smuzhiyun },
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun .start = IRQ_IXP4XX_UART2,
88*4882a593Smuzhiyun .end = IRQ_IXP4XX_UART2,
89*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
90*4882a593Smuzhiyun },
91*4882a593Smuzhiyun { },
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static struct plat_serial8250_port gtwx5715_uart_platform_data[] = {
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun .mapbase = IXP4XX_UART2_BASE_PHYS,
98*4882a593Smuzhiyun .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
99*4882a593Smuzhiyun .irq = IRQ_IXP4XX_UART2,
100*4882a593Smuzhiyun .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
101*4882a593Smuzhiyun .iotype = UPIO_MEM,
102*4882a593Smuzhiyun .regshift = 2,
103*4882a593Smuzhiyun .uartclk = IXP4XX_UART_XTAL,
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun { },
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static struct platform_device gtwx5715_uart_device = {
109*4882a593Smuzhiyun .name = "serial8250",
110*4882a593Smuzhiyun .id = PLAT8250_DEV_PLATFORM,
111*4882a593Smuzhiyun .dev = {
112*4882a593Smuzhiyun .platform_data = gtwx5715_uart_platform_data,
113*4882a593Smuzhiyun },
114*4882a593Smuzhiyun .num_resources = 2,
115*4882a593Smuzhiyun .resource = gtwx5715_uart_resources,
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static struct flash_platform_data gtwx5715_flash_data = {
119*4882a593Smuzhiyun .map_name = "cfi_probe",
120*4882a593Smuzhiyun .width = 2,
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun static struct resource gtwx5715_flash_resource = {
124*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static struct platform_device gtwx5715_flash = {
128*4882a593Smuzhiyun .name = "IXP4XX-Flash",
129*4882a593Smuzhiyun .id = 0,
130*4882a593Smuzhiyun .dev = {
131*4882a593Smuzhiyun .platform_data = >wx5715_flash_data,
132*4882a593Smuzhiyun },
133*4882a593Smuzhiyun .num_resources = 1,
134*4882a593Smuzhiyun .resource = >wx5715_flash_resource,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static struct platform_device *gtwx5715_devices[] __initdata = {
138*4882a593Smuzhiyun >wx5715_uart_device,
139*4882a593Smuzhiyun >wx5715_flash,
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
gtwx5715_init(void)142*4882a593Smuzhiyun static void __init gtwx5715_init(void)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun ixp4xx_sys_init();
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun gtwx5715_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
147*4882a593Smuzhiyun gtwx5715_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun platform_add_devices(gtwx5715_devices, ARRAY_SIZE(gtwx5715_devices));
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
154*4882a593Smuzhiyun /* Maintainer: George Joseph */
155*4882a593Smuzhiyun .map_io = ixp4xx_map_io,
156*4882a593Smuzhiyun .init_early = ixp4xx_init_early,
157*4882a593Smuzhiyun .init_irq = ixp4xx_init_irq,
158*4882a593Smuzhiyun .init_time = ixp4xx_timer_init,
159*4882a593Smuzhiyun .atag_offset = 0x100,
160*4882a593Smuzhiyun .init_machine = gtwx5715_init,
161*4882a593Smuzhiyun #if defined(CONFIG_PCI)
162*4882a593Smuzhiyun .dma_zone_size = SZ_64M,
163*4882a593Smuzhiyun #endif
164*4882a593Smuzhiyun .restart = ixp4xx_restart,
165*4882a593Smuzhiyun MACHINE_END
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun
168