1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/gtwx5715-pci.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Gemtek GTWX5715 (Linksys WRV54G) board setup
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2004 George T. Joseph
8*4882a593Smuzhiyun * Derived from Coyote
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <asm/mach-types.h>
16*4882a593Smuzhiyun #include <mach/hardware.h>
17*4882a593Smuzhiyun #include <asm/mach/pci.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "irqs.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define SLOT0_DEVID 0
22*4882a593Smuzhiyun #define SLOT1_DEVID 1
23*4882a593Smuzhiyun #define INTA 10 /* slot 1 has INTA and INTB crossed */
24*4882a593Smuzhiyun #define INTB 11
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * Slot 0 isn't actually populated with a card connector but
28*4882a593Smuzhiyun * we initialize it anyway in case a future version has the
29*4882a593Smuzhiyun * slot populated or someone with good soldering skills has
30*4882a593Smuzhiyun * some free time.
31*4882a593Smuzhiyun */
gtwx5715_pci_preinit(void)32*4882a593Smuzhiyun void __init gtwx5715_pci_preinit(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
35*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
36*4882a593Smuzhiyun ixp4xx_pci_preinit();
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun
gtwx5715_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)40*4882a593Smuzhiyun static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun int rc = -1;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun if ((slot == SLOT0_DEVID && pin == 1) ||
45*4882a593Smuzhiyun (slot == SLOT1_DEVID && pin == 2))
46*4882a593Smuzhiyun rc = IXP4XX_GPIO_IRQ(INTA);
47*4882a593Smuzhiyun else if ((slot == SLOT0_DEVID && pin == 2) ||
48*4882a593Smuzhiyun (slot == SLOT1_DEVID && pin == 1))
49*4882a593Smuzhiyun rc = IXP4XX_GPIO_IRQ(INTB);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
52*4882a593Smuzhiyun __func__, slot, pin, rc);
53*4882a593Smuzhiyun return rc;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun struct hw_pci gtwx5715_pci __initdata = {
57*4882a593Smuzhiyun .nr_controllers = 1,
58*4882a593Smuzhiyun .ops = &ixp4xx_ops,
59*4882a593Smuzhiyun .preinit = gtwx5715_pci_preinit,
60*4882a593Smuzhiyun .setup = ixp4xx_setup,
61*4882a593Smuzhiyun .map_irq = gtwx5715_map_irq,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
gtwx5715_pci_init(void)64*4882a593Smuzhiyun int __init gtwx5715_pci_init(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun if (machine_is_gtwx5715())
67*4882a593Smuzhiyun pci_common_init(>wx5715_pci);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun subsys_initcall(gtwx5715_pci_init);
73