1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arch/mach-ixp4xx/fsg-pci.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * FSG board-level PCI initialization
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Rod Whitby <rod@whitby.id.au>
8*4882a593Smuzhiyun * Maintainer: http://www.nslu2-linux.org/
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * based on ixdp425-pci.c:
11*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation.
12*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/irq.h>
18*4882a593Smuzhiyun #include <asm/mach/pci.h>
19*4882a593Smuzhiyun #include <asm/mach-types.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "irqs.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define MAX_DEV 3
24*4882a593Smuzhiyun #define IRQ_LINES 3
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* PCI controller GPIO to IRQ pin mappings */
27*4882a593Smuzhiyun #define INTA 6
28*4882a593Smuzhiyun #define INTB 7
29*4882a593Smuzhiyun #define INTC 5
30*4882a593Smuzhiyun
fsg_pci_preinit(void)31*4882a593Smuzhiyun void __init fsg_pci_preinit(void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
34*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
35*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
36*4882a593Smuzhiyun ixp4xx_pci_preinit();
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
fsg_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)39*4882a593Smuzhiyun static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun static int pci_irq_table[IRQ_LINES] = {
42*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTC),
43*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTB),
44*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTA),
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun int irq = -1;
48*4882a593Smuzhiyun slot -= 11;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
51*4882a593Smuzhiyun irq = pci_irq_table[slot - 1];
52*4882a593Smuzhiyun printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
53*4882a593Smuzhiyun __func__, slot, pin, irq);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return irq;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun struct hw_pci fsg_pci __initdata = {
59*4882a593Smuzhiyun .nr_controllers = 1,
60*4882a593Smuzhiyun .ops = &ixp4xx_ops,
61*4882a593Smuzhiyun .preinit = fsg_pci_preinit,
62*4882a593Smuzhiyun .setup = ixp4xx_setup,
63*4882a593Smuzhiyun .map_irq = fsg_map_irq,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
fsg_pci_init(void)66*4882a593Smuzhiyun int __init fsg_pci_init(void)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun if (machine_is_fsg())
69*4882a593Smuzhiyun pci_common_init(&fsg_pci);
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun subsys_initcall(fsg_pci_init);
74