1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * DSM-G600 board-level PCI initialization
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2006 Tower Technologies
6*4882a593Smuzhiyun * Author: Alessandro Zummo <a.zummo@towertech.it>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * based on ixdp425-pci.c:
9*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation.
10*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Maintainer: http://www.nslu2-linux.org/
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/irq.h>
18*4882a593Smuzhiyun #include <asm/mach/pci.h>
19*4882a593Smuzhiyun #include <asm/mach-types.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "irqs.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define MAX_DEV 4
24*4882a593Smuzhiyun #define IRQ_LINES 3
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* PCI controller GPIO to IRQ pin mappings */
27*4882a593Smuzhiyun #define INTA 11
28*4882a593Smuzhiyun #define INTB 10
29*4882a593Smuzhiyun #define INTC 9
30*4882a593Smuzhiyun #define INTD 8
31*4882a593Smuzhiyun #define INTE 7
32*4882a593Smuzhiyun #define INTF 6
33*4882a593Smuzhiyun
dsmg600_pci_preinit(void)34*4882a593Smuzhiyun void __init dsmg600_pci_preinit(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
37*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
38*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
39*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
40*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
41*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
42*4882a593Smuzhiyun ixp4xx_pci_preinit();
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
dsmg600_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)45*4882a593Smuzhiyun static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
48*4882a593Smuzhiyun { IXP4XX_GPIO_IRQ(INTE), -1, -1 },
49*4882a593Smuzhiyun { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
50*4882a593Smuzhiyun { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
51*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTD) },
52*4882a593Smuzhiyun { IXP4XX_GPIO_IRQ(INTF), -1, -1 },
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
56*4882a593Smuzhiyun return pci_irq_table[slot - 1][pin - 1];
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return -1;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun struct hw_pci __initdata dsmg600_pci = {
62*4882a593Smuzhiyun .nr_controllers = 1,
63*4882a593Smuzhiyun .ops = &ixp4xx_ops,
64*4882a593Smuzhiyun .preinit = dsmg600_pci_preinit,
65*4882a593Smuzhiyun .setup = ixp4xx_setup,
66*4882a593Smuzhiyun .map_irq = dsmg600_map_irq,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
dsmg600_pci_init(void)69*4882a593Smuzhiyun int __init dsmg600_pci_init(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun if (machine_is_dsmg600())
72*4882a593Smuzhiyun pci_common_init(&dsmg600_pci);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun subsys_initcall(dsmg600_pci_init);
78