1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ixp4xx/avila-pci.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Gateworks Avila board-level PCI initialization
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Michael-Luke Jones <mlj28@cam.ac.uk>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on ixdp-pci.c
10*4882a593Smuzhiyun * Copyright (C) 2002 Intel Corporation.
11*4882a593Smuzhiyun * Copyright (C) 2003-2004 MontaVista Software, Inc.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Maintainer: Deepak Saxena <dsaxena@plexity.net>
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/irq.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <asm/mach/pci.h>
22*4882a593Smuzhiyun #include <asm/irq.h>
23*4882a593Smuzhiyun #include <mach/hardware.h>
24*4882a593Smuzhiyun #include <asm/mach-types.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "irqs.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define AVILA_MAX_DEV 4
29*4882a593Smuzhiyun #define LOFT_MAX_DEV 6
30*4882a593Smuzhiyun #define IRQ_LINES 4
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* PCI controller GPIO to IRQ pin mappings */
33*4882a593Smuzhiyun #define INTA 11
34*4882a593Smuzhiyun #define INTB 10
35*4882a593Smuzhiyun #define INTC 9
36*4882a593Smuzhiyun #define INTD 8
37*4882a593Smuzhiyun
avila_pci_preinit(void)38*4882a593Smuzhiyun void __init avila_pci_preinit(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
41*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
42*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
43*4882a593Smuzhiyun irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
44*4882a593Smuzhiyun ixp4xx_pci_preinit();
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
avila_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)47*4882a593Smuzhiyun static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun static int pci_irq_table[IRQ_LINES] = {
50*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTA),
51*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTB),
52*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTC),
53*4882a593Smuzhiyun IXP4XX_GPIO_IRQ(INTD)
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (slot >= 1 &&
57*4882a593Smuzhiyun slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) &&
58*4882a593Smuzhiyun pin >= 1 && pin <= IRQ_LINES)
59*4882a593Smuzhiyun return pci_irq_table[(slot + pin - 2) % 4];
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return -1;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct hw_pci avila_pci __initdata = {
65*4882a593Smuzhiyun .nr_controllers = 1,
66*4882a593Smuzhiyun .ops = &ixp4xx_ops,
67*4882a593Smuzhiyun .preinit = avila_pci_preinit,
68*4882a593Smuzhiyun .setup = ixp4xx_setup,
69*4882a593Smuzhiyun .map_irq = avila_map_irq,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
avila_pci_init(void)72*4882a593Smuzhiyun int __init avila_pci_init(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun if (machine_is_avila() || machine_is_loft())
75*4882a593Smuzhiyun pci_common_init(&avila_pci);
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun subsys_initcall(avila_pci_init);
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