1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-iop32x/irq.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Generic IOP32X IRQ handling functionality
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Rory Bolt <rorybolt@pacbell.net>
8*4882a593Smuzhiyun * Copyright (C) 2002 Rory Bolt
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/list.h>
14*4882a593Smuzhiyun #include <asm/mach/irq.h>
15*4882a593Smuzhiyun #include <asm/irq.h>
16*4882a593Smuzhiyun #include <asm/mach-types.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "hardware.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static u32 iop32x_mask;
21*4882a593Smuzhiyun
intctl_write(u32 val)22*4882a593Smuzhiyun static void intctl_write(u32 val)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
intstr_write(u32 val)27*4882a593Smuzhiyun static void intstr_write(u32 val)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static void
iop32x_irq_mask(struct irq_data * d)33*4882a593Smuzhiyun iop32x_irq_mask(struct irq_data *d)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun iop32x_mask &= ~(1 << (d->irq - 1));
36*4882a593Smuzhiyun intctl_write(iop32x_mask);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static void
iop32x_irq_unmask(struct irq_data * d)40*4882a593Smuzhiyun iop32x_irq_unmask(struct irq_data *d)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun iop32x_mask |= 1 << (d->irq - 1);
43*4882a593Smuzhiyun intctl_write(iop32x_mask);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct irq_chip ext_chip = {
47*4882a593Smuzhiyun .name = "IOP32x",
48*4882a593Smuzhiyun .irq_ack = iop32x_irq_mask,
49*4882a593Smuzhiyun .irq_mask = iop32x_irq_mask,
50*4882a593Smuzhiyun .irq_unmask = iop32x_irq_unmask,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
iop32x_init_irq(void)53*4882a593Smuzhiyun void __init iop32x_init_irq(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun int i;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun iop_init_cp6_handler();
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun intctl_write(0);
60*4882a593Smuzhiyun intstr_write(0);
61*4882a593Smuzhiyun if (machine_is_glantank() ||
62*4882a593Smuzhiyun machine_is_iq80321() ||
63*4882a593Smuzhiyun machine_is_iq31244() ||
64*4882a593Smuzhiyun machine_is_n2100() ||
65*4882a593Smuzhiyun machine_is_em7210())
66*4882a593Smuzhiyun *IOP3XX_PCIIRSR = 0x0f;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun for (i = 1; i < NR_IRQS; i++) {
69*4882a593Smuzhiyun irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
70*4882a593Smuzhiyun irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun }
73