xref: /OK3568_Linux_fs/kernel/arch/arm/mach-iop32x/iq31244.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * arch/arm/mach-iop32x/iq31244.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Board support code for the Intel EP80219 and IQ31244 platforms.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Rory Bolt <rorybolt@pacbell.net>
8*4882a593Smuzhiyun  * Copyright (C) 2002 Rory Bolt
9*4882a593Smuzhiyun  * Copyright 2003 (c) MontaVista, Software, Inc.
10*4882a593Smuzhiyun  * Copyright (C) 2004 Intel Corp.
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/mm.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/pm.h>
19*4882a593Smuzhiyun #include <linux/string.h>
20*4882a593Smuzhiyun #include <linux/serial_core.h>
21*4882a593Smuzhiyun #include <linux/serial_8250.h>
22*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
23*4882a593Smuzhiyun #include <linux/platform_device.h>
24*4882a593Smuzhiyun #include <linux/io.h>
25*4882a593Smuzhiyun #include <linux/gpio/machine.h>
26*4882a593Smuzhiyun #include <asm/cputype.h>
27*4882a593Smuzhiyun #include <asm/irq.h>
28*4882a593Smuzhiyun #include <asm/mach/arch.h>
29*4882a593Smuzhiyun #include <asm/mach/map.h>
30*4882a593Smuzhiyun #include <asm/mach/pci.h>
31*4882a593Smuzhiyun #include <asm/mach/time.h>
32*4882a593Smuzhiyun #include <asm/mach-types.h>
33*4882a593Smuzhiyun #include <asm/page.h>
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #include "hardware.h"
36*4882a593Smuzhiyun #include "irqs.h"
37*4882a593Smuzhiyun #include "gpio-iop32x.h"
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun  * Until March of 2007 iq31244 platforms and ep80219 platforms shared the
41*4882a593Smuzhiyun  * same machine id, and the processor type was used to select board type.
42*4882a593Smuzhiyun  * However this assumption breaks for an iq80219 board which is an iop219
43*4882a593Smuzhiyun  * processor on an iq31244 board.  The force_ep80219 flag has been added
44*4882a593Smuzhiyun  * for old boot loaders using the iq31244 machine id for an ep80219 platform.
45*4882a593Smuzhiyun  */
46*4882a593Smuzhiyun static int force_ep80219;
47*4882a593Smuzhiyun 
is_80219(void)48*4882a593Smuzhiyun static int is_80219(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
is_ep80219(void)53*4882a593Smuzhiyun static int is_ep80219(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	if (machine_is_ep80219() || force_ep80219)
56*4882a593Smuzhiyun 		return 1;
57*4882a593Smuzhiyun 	else
58*4882a593Smuzhiyun 		return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun  * EP80219/IQ31244 timer tick configuration.
64*4882a593Smuzhiyun  */
iq31244_timer_init(void)65*4882a593Smuzhiyun static void __init iq31244_timer_init(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	if (is_ep80219()) {
68*4882a593Smuzhiyun 		/* 33.333 MHz crystal.  */
69*4882a593Smuzhiyun 		iop_init_time(200000000);
70*4882a593Smuzhiyun 	} else {
71*4882a593Smuzhiyun 		/* 33.000 MHz crystal.  */
72*4882a593Smuzhiyun 		iop_init_time(198000000);
73*4882a593Smuzhiyun 	}
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun  * IQ31244 I/O.
79*4882a593Smuzhiyun  */
80*4882a593Smuzhiyun static struct map_desc iq31244_io_desc[] __initdata = {
81*4882a593Smuzhiyun 	{	/* on-board devices */
82*4882a593Smuzhiyun 		.virtual	= IQ31244_UART,
83*4882a593Smuzhiyun 		.pfn		= __phys_to_pfn(IQ31244_UART),
84*4882a593Smuzhiyun 		.length		= 0x00100000,
85*4882a593Smuzhiyun 		.type		= MT_DEVICE,
86*4882a593Smuzhiyun 	},
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
iq31244_map_io(void)89*4882a593Smuzhiyun void __init iq31244_map_io(void)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	iop3xx_map_io();
92*4882a593Smuzhiyun 	iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun  * EP80219/IQ31244 PCI.
98*4882a593Smuzhiyun  */
99*4882a593Smuzhiyun static int __init
ep80219_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)100*4882a593Smuzhiyun ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	int irq;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	if (slot == 0) {
105*4882a593Smuzhiyun 		/* CFlash */
106*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT1;
107*4882a593Smuzhiyun 	} else if (slot == 1) {
108*4882a593Smuzhiyun 		/* 82551 Pro 100 */
109*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT0;
110*4882a593Smuzhiyun 	} else if (slot == 2) {
111*4882a593Smuzhiyun 		/* PCI-X Slot */
112*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT3;
113*4882a593Smuzhiyun 	} else if (slot == 3) {
114*4882a593Smuzhiyun 		/* SATA */
115*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT2;
116*4882a593Smuzhiyun 	} else {
117*4882a593Smuzhiyun 		printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
118*4882a593Smuzhiyun 			"device PCI:%d:%d:%d\n", dev->bus->number,
119*4882a593Smuzhiyun 			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
120*4882a593Smuzhiyun 		irq = -1;
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	return irq;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun static struct hw_pci ep80219_pci __initdata = {
127*4882a593Smuzhiyun 	.nr_controllers = 1,
128*4882a593Smuzhiyun 	.ops		= &iop3xx_ops,
129*4882a593Smuzhiyun 	.setup		= iop3xx_pci_setup,
130*4882a593Smuzhiyun 	.preinit	= iop3xx_pci_preinit,
131*4882a593Smuzhiyun 	.map_irq	= ep80219_pci_map_irq,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun static int __init
iq31244_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)135*4882a593Smuzhiyun iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	int irq;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	if (slot == 0) {
140*4882a593Smuzhiyun 		/* CFlash */
141*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT1;
142*4882a593Smuzhiyun 	} else if (slot == 1) {
143*4882a593Smuzhiyun 		/* SATA */
144*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT2;
145*4882a593Smuzhiyun 	} else if (slot == 2) {
146*4882a593Smuzhiyun 		/* PCI-X Slot */
147*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT3;
148*4882a593Smuzhiyun 	} else if (slot == 3) {
149*4882a593Smuzhiyun 		/* 82546 GigE */
150*4882a593Smuzhiyun 		irq = IRQ_IOP32X_XINT0;
151*4882a593Smuzhiyun 	} else {
152*4882a593Smuzhiyun 		printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
153*4882a593Smuzhiyun 			"device PCI:%d:%d:%d\n", dev->bus->number,
154*4882a593Smuzhiyun 			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
155*4882a593Smuzhiyun 		irq = -1;
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	return irq;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static struct hw_pci iq31244_pci __initdata = {
162*4882a593Smuzhiyun 	.nr_controllers = 1,
163*4882a593Smuzhiyun 	.ops		= &iop3xx_ops,
164*4882a593Smuzhiyun 	.setup		= iop3xx_pci_setup,
165*4882a593Smuzhiyun 	.preinit	= iop3xx_pci_preinit,
166*4882a593Smuzhiyun 	.map_irq	= iq31244_pci_map_irq,
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
iq31244_pci_init(void)169*4882a593Smuzhiyun static int __init iq31244_pci_init(void)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	if (is_ep80219())
172*4882a593Smuzhiyun 		pci_common_init(&ep80219_pci);
173*4882a593Smuzhiyun 	else if (machine_is_iq31244()) {
174*4882a593Smuzhiyun 		if (is_80219()) {
175*4882a593Smuzhiyun 			printk("note: iq31244 board type has been selected\n");
176*4882a593Smuzhiyun 			printk("note: to select ep80219 operation:\n");
177*4882a593Smuzhiyun 			printk("\t1/ specify \"force_ep80219\" on the kernel"
178*4882a593Smuzhiyun 				" command line\n");
179*4882a593Smuzhiyun 			printk("\t2/ update boot loader to pass"
180*4882a593Smuzhiyun 				" the ep80219 id: %d\n", MACH_TYPE_EP80219);
181*4882a593Smuzhiyun 		}
182*4882a593Smuzhiyun 		pci_common_init(&iq31244_pci);
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	return 0;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun subsys_initcall(iq31244_pci_init);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun /*
192*4882a593Smuzhiyun  * IQ31244 machine initialisation.
193*4882a593Smuzhiyun  */
194*4882a593Smuzhiyun static struct physmap_flash_data iq31244_flash_data = {
195*4882a593Smuzhiyun 	.width		= 2,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun static struct resource iq31244_flash_resource = {
199*4882a593Smuzhiyun 	.start		= 0xf0000000,
200*4882a593Smuzhiyun 	.end		= 0xf07fffff,
201*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun static struct platform_device iq31244_flash_device = {
205*4882a593Smuzhiyun 	.name		= "physmap-flash",
206*4882a593Smuzhiyun 	.id		= 0,
207*4882a593Smuzhiyun 	.dev		= {
208*4882a593Smuzhiyun 		.platform_data	= &iq31244_flash_data,
209*4882a593Smuzhiyun 	},
210*4882a593Smuzhiyun 	.num_resources	= 1,
211*4882a593Smuzhiyun 	.resource	= &iq31244_flash_resource,
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun static struct plat_serial8250_port iq31244_serial_port[] = {
215*4882a593Smuzhiyun 	{
216*4882a593Smuzhiyun 		.mapbase	= IQ31244_UART,
217*4882a593Smuzhiyun 		.membase	= (char *)IQ31244_UART,
218*4882a593Smuzhiyun 		.irq		= IRQ_IOP32X_XINT1,
219*4882a593Smuzhiyun 		.flags		= UPF_SKIP_TEST,
220*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
221*4882a593Smuzhiyun 		.regshift	= 0,
222*4882a593Smuzhiyun 		.uartclk	= 1843200,
223*4882a593Smuzhiyun 	},
224*4882a593Smuzhiyun 	{ },
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static struct resource iq31244_uart_resource = {
228*4882a593Smuzhiyun 	.start		= IQ31244_UART,
229*4882a593Smuzhiyun 	.end		= IQ31244_UART + 7,
230*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static struct platform_device iq31244_serial_device = {
234*4882a593Smuzhiyun 	.name		= "serial8250",
235*4882a593Smuzhiyun 	.id		= PLAT8250_DEV_PLATFORM,
236*4882a593Smuzhiyun 	.dev		= {
237*4882a593Smuzhiyun 		.platform_data		= iq31244_serial_port,
238*4882a593Smuzhiyun 	},
239*4882a593Smuzhiyun 	.num_resources	= 1,
240*4882a593Smuzhiyun 	.resource	= &iq31244_uart_resource,
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /*
244*4882a593Smuzhiyun  * This function will send a SHUTDOWN_COMPLETE message to the PIC
245*4882a593Smuzhiyun  * controller over I2C.  We are not using the i2c subsystem since
246*4882a593Smuzhiyun  * we are going to power off and it may be removed
247*4882a593Smuzhiyun  */
ep80219_power_off(void)248*4882a593Smuzhiyun void ep80219_power_off(void)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun 	/*
251*4882a593Smuzhiyun 	 * Send the Address byte w/ the start condition
252*4882a593Smuzhiyun 	 */
253*4882a593Smuzhiyun 	*IOP3XX_IDBR1 = 0x60;
254*4882a593Smuzhiyun 	*IOP3XX_ICR1 = 0xE9;
255*4882a593Smuzhiyun 	mdelay(1);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/*
258*4882a593Smuzhiyun 	 * Send the START_MSG byte w/ no start or stop condition
259*4882a593Smuzhiyun 	 */
260*4882a593Smuzhiyun 	*IOP3XX_IDBR1 = 0x0F;
261*4882a593Smuzhiyun 	*IOP3XX_ICR1 = 0xE8;
262*4882a593Smuzhiyun 	mdelay(1);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	/*
265*4882a593Smuzhiyun 	 * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
266*4882a593Smuzhiyun 	 * stop condition
267*4882a593Smuzhiyun 	 */
268*4882a593Smuzhiyun 	*IOP3XX_IDBR1 = 0x03;
269*4882a593Smuzhiyun 	*IOP3XX_ICR1 = 0xE8;
270*4882a593Smuzhiyun 	mdelay(1);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/*
273*4882a593Smuzhiyun 	 * Send an ignored byte w/ stop condition
274*4882a593Smuzhiyun 	 */
275*4882a593Smuzhiyun 	*IOP3XX_IDBR1 = 0x00;
276*4882a593Smuzhiyun 	*IOP3XX_ICR1 = 0xEA;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	while (1)
279*4882a593Smuzhiyun 		;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
iq31244_init_machine(void)282*4882a593Smuzhiyun static void __init iq31244_init_machine(void)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun 	register_iop32x_gpio();
285*4882a593Smuzhiyun 	gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
286*4882a593Smuzhiyun 	gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup);
287*4882a593Smuzhiyun 	platform_device_register(&iop3xx_i2c0_device);
288*4882a593Smuzhiyun 	platform_device_register(&iop3xx_i2c1_device);
289*4882a593Smuzhiyun 	platform_device_register(&iq31244_flash_device);
290*4882a593Smuzhiyun 	platform_device_register(&iq31244_serial_device);
291*4882a593Smuzhiyun 	platform_device_register(&iop3xx_dma_0_channel);
292*4882a593Smuzhiyun 	platform_device_register(&iop3xx_dma_1_channel);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	if (is_ep80219())
295*4882a593Smuzhiyun 		pm_power_off = ep80219_power_off;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	if (!is_80219())
298*4882a593Smuzhiyun 		platform_device_register(&iop3xx_aau_channel);
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
force_ep80219_setup(char * str)301*4882a593Smuzhiyun static int __init force_ep80219_setup(char *str)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	force_ep80219 = 1;
304*4882a593Smuzhiyun 	return 1;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun __setup("force_ep80219", force_ep80219_setup);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun MACHINE_START(IQ31244, "Intel IQ31244")
310*4882a593Smuzhiyun 	/* Maintainer: Intel Corp. */
311*4882a593Smuzhiyun 	.atag_offset	= 0x100,
312*4882a593Smuzhiyun 	.map_io		= iq31244_map_io,
313*4882a593Smuzhiyun 	.init_irq	= iop32x_init_irq,
314*4882a593Smuzhiyun 	.init_time	= iq31244_timer_init,
315*4882a593Smuzhiyun 	.init_machine	= iq31244_init_machine,
316*4882a593Smuzhiyun 	.restart	= iop3xx_restart,
317*4882a593Smuzhiyun MACHINE_END
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /* There should have been an ep80219 machine identifier from the beginning.
320*4882a593Smuzhiyun  * Boot roms older than March 2007 do not know the ep80219 machine id.  Pass
321*4882a593Smuzhiyun  * "force_ep80219" on the kernel command line, otherwise iq31244 operation
322*4882a593Smuzhiyun  * will be selected.
323*4882a593Smuzhiyun  */
324*4882a593Smuzhiyun MACHINE_START(EP80219, "Intel EP80219")
325*4882a593Smuzhiyun 	/* Maintainer: Intel Corp. */
326*4882a593Smuzhiyun 	.atag_offset	= 0x100,
327*4882a593Smuzhiyun 	.map_io		= iq31244_map_io,
328*4882a593Smuzhiyun 	.init_irq	= iop32x_init_irq,
329*4882a593Smuzhiyun 	.init_time	= iq31244_timer_init,
330*4882a593Smuzhiyun 	.init_machine	= iq31244_init_machine,
331*4882a593Smuzhiyun 	.restart	= iop3xx_restart,
332*4882a593Smuzhiyun MACHINE_END
333