xref: /OK3568_Linux_fs/kernel/arch/arm/mach-iop32x/glantank.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * arch/arm/mach-iop32x/glantank.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Board support code for the GLAN Tank.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2006, 2007 Martin Michlmayr <tbm@cyrius.com>
8*4882a593Smuzhiyun  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/mm.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/f75375s.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/pm.h>
17*4882a593Smuzhiyun #include <linux/string.h>
18*4882a593Smuzhiyun #include <linux/serial_core.h>
19*4882a593Smuzhiyun #include <linux/serial_8250.h>
20*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
21*4882a593Smuzhiyun #include <linux/i2c.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/io.h>
24*4882a593Smuzhiyun #include <linux/gpio/machine.h>
25*4882a593Smuzhiyun #include <asm/irq.h>
26*4882a593Smuzhiyun #include <asm/mach/arch.h>
27*4882a593Smuzhiyun #include <asm/mach/map.h>
28*4882a593Smuzhiyun #include <asm/mach/pci.h>
29*4882a593Smuzhiyun #include <asm/mach/time.h>
30*4882a593Smuzhiyun #include <asm/mach-types.h>
31*4882a593Smuzhiyun #include <asm/page.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "hardware.h"
34*4882a593Smuzhiyun #include "gpio-iop32x.h"
35*4882a593Smuzhiyun #include "irqs.h"
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun  * GLAN Tank timer tick configuration.
39*4882a593Smuzhiyun  */
glantank_timer_init(void)40*4882a593Smuzhiyun static void __init glantank_timer_init(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	/* 33.333 MHz crystal.  */
43*4882a593Smuzhiyun 	iop_init_time(200000000);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun  * GLAN Tank I/O.
49*4882a593Smuzhiyun  */
50*4882a593Smuzhiyun static struct map_desc glantank_io_desc[] __initdata = {
51*4882a593Smuzhiyun 	{	/* on-board devices */
52*4882a593Smuzhiyun 		.virtual	= GLANTANK_UART,
53*4882a593Smuzhiyun 		.pfn		= __phys_to_pfn(GLANTANK_UART),
54*4882a593Smuzhiyun 		.length		= 0x00100000,
55*4882a593Smuzhiyun 		.type		= MT_DEVICE
56*4882a593Smuzhiyun 	},
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
glantank_map_io(void)59*4882a593Smuzhiyun void __init glantank_map_io(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	iop3xx_map_io();
62*4882a593Smuzhiyun 	iotable_init(glantank_io_desc, ARRAY_SIZE(glantank_io_desc));
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun  * GLAN Tank PCI.
68*4882a593Smuzhiyun  */
69*4882a593Smuzhiyun #define INTA	IRQ_IOP32X_XINT0
70*4882a593Smuzhiyun #define INTB	IRQ_IOP32X_XINT1
71*4882a593Smuzhiyun #define INTC	IRQ_IOP32X_XINT2
72*4882a593Smuzhiyun #define INTD	IRQ_IOP32X_XINT3
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun static int __init
glantank_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)75*4882a593Smuzhiyun glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	static int pci_irq_table[][4] = {
78*4882a593Smuzhiyun 		/*
79*4882a593Smuzhiyun 		 * PCI IDSEL/INTPIN->INTLINE
80*4882a593Smuzhiyun 		 * A       B       C       D
81*4882a593Smuzhiyun 		 */
82*4882a593Smuzhiyun 		{INTD, INTD, INTD, INTD}, /* UART (8250) */
83*4882a593Smuzhiyun 		{INTA, INTA, INTA, INTA}, /* Ethernet (E1000) */
84*4882a593Smuzhiyun 		{INTB, INTB, INTB, INTB}, /* IDE (AEC6280R) */
85*4882a593Smuzhiyun 		{INTC, INTC, INTC, INTC}, /* USB (NEC) */
86*4882a593Smuzhiyun 	};
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	BUG_ON(pin < 1 || pin > 4);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	return pci_irq_table[slot % 4][pin - 1];
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun static struct hw_pci glantank_pci __initdata = {
94*4882a593Smuzhiyun 	.nr_controllers = 1,
95*4882a593Smuzhiyun 	.ops		= &iop3xx_ops,
96*4882a593Smuzhiyun 	.setup		= iop3xx_pci_setup,
97*4882a593Smuzhiyun 	.preinit	= iop3xx_pci_preinit,
98*4882a593Smuzhiyun 	.map_irq	= glantank_pci_map_irq,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
glantank_pci_init(void)101*4882a593Smuzhiyun static int __init glantank_pci_init(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	if (machine_is_glantank())
104*4882a593Smuzhiyun 		pci_common_init(&glantank_pci);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun subsys_initcall(glantank_pci_init);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun  * GLAN Tank machine initialization.
114*4882a593Smuzhiyun  */
115*4882a593Smuzhiyun static struct physmap_flash_data glantank_flash_data = {
116*4882a593Smuzhiyun 	.width		= 2,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun static struct resource glantank_flash_resource = {
120*4882a593Smuzhiyun 	.start		= 0xf0000000,
121*4882a593Smuzhiyun 	.end		= 0xf007ffff,
122*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun static struct platform_device glantank_flash_device = {
126*4882a593Smuzhiyun 	.name		= "physmap-flash",
127*4882a593Smuzhiyun 	.id		= 0,
128*4882a593Smuzhiyun 	.dev		= {
129*4882a593Smuzhiyun 		.platform_data	= &glantank_flash_data,
130*4882a593Smuzhiyun 	},
131*4882a593Smuzhiyun 	.num_resources	= 1,
132*4882a593Smuzhiyun 	.resource	= &glantank_flash_resource,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun static struct plat_serial8250_port glantank_serial_port[] = {
136*4882a593Smuzhiyun 	{
137*4882a593Smuzhiyun 		.mapbase	= GLANTANK_UART,
138*4882a593Smuzhiyun 		.membase	= (char *)GLANTANK_UART,
139*4882a593Smuzhiyun 		.irq		= IRQ_IOP32X_XINT3,
140*4882a593Smuzhiyun 		.flags		= UPF_SKIP_TEST,
141*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
142*4882a593Smuzhiyun 		.regshift	= 0,
143*4882a593Smuzhiyun 		.uartclk	= 1843200,
144*4882a593Smuzhiyun 	},
145*4882a593Smuzhiyun 	{ },
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static struct resource glantank_uart_resource = {
149*4882a593Smuzhiyun 	.start		= GLANTANK_UART,
150*4882a593Smuzhiyun 	.end		= GLANTANK_UART + 7,
151*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun static struct platform_device glantank_serial_device = {
155*4882a593Smuzhiyun 	.name		= "serial8250",
156*4882a593Smuzhiyun 	.id		= PLAT8250_DEV_PLATFORM,
157*4882a593Smuzhiyun 	.dev		= {
158*4882a593Smuzhiyun 		.platform_data		= glantank_serial_port,
159*4882a593Smuzhiyun 	},
160*4882a593Smuzhiyun 	.num_resources	= 1,
161*4882a593Smuzhiyun 	.resource	= &glantank_uart_resource,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun static struct f75375s_platform_data glantank_f75375s = {
165*4882a593Smuzhiyun 	.pwm		= { 255, 255 },
166*4882a593Smuzhiyun 	.pwm_enable	= { 0, 0 },
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static struct i2c_board_info __initdata glantank_i2c_devices[] = {
170*4882a593Smuzhiyun 	{
171*4882a593Smuzhiyun 		I2C_BOARD_INFO("rs5c372a", 0x32),
172*4882a593Smuzhiyun 	},
173*4882a593Smuzhiyun 	{
174*4882a593Smuzhiyun 		I2C_BOARD_INFO("f75375", 0x2e),
175*4882a593Smuzhiyun 		.platform_data = &glantank_f75375s,
176*4882a593Smuzhiyun 	},
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
glantank_power_off(void)179*4882a593Smuzhiyun static void glantank_power_off(void)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	__raw_writeb(0x01, IOMEM(0xfe8d0004));
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	while (1)
184*4882a593Smuzhiyun 		;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
glantank_init_machine(void)187*4882a593Smuzhiyun static void __init glantank_init_machine(void)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	register_iop32x_gpio();
190*4882a593Smuzhiyun 	gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
191*4882a593Smuzhiyun 	gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup);
192*4882a593Smuzhiyun 	platform_device_register(&iop3xx_i2c0_device);
193*4882a593Smuzhiyun 	platform_device_register(&iop3xx_i2c1_device);
194*4882a593Smuzhiyun 	platform_device_register(&glantank_flash_device);
195*4882a593Smuzhiyun 	platform_device_register(&glantank_serial_device);
196*4882a593Smuzhiyun 	platform_device_register(&iop3xx_dma_0_channel);
197*4882a593Smuzhiyun 	platform_device_register(&iop3xx_dma_1_channel);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	i2c_register_board_info(0, glantank_i2c_devices,
200*4882a593Smuzhiyun 		ARRAY_SIZE(glantank_i2c_devices));
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	pm_power_off = glantank_power_off;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun MACHINE_START(GLANTANK, "GLAN Tank")
206*4882a593Smuzhiyun 	/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
207*4882a593Smuzhiyun 	.atag_offset	= 0x100,
208*4882a593Smuzhiyun 	.map_io		= glantank_map_io,
209*4882a593Smuzhiyun 	.init_irq	= iop32x_init_irq,
210*4882a593Smuzhiyun 	.init_time	= glantank_timer_init,
211*4882a593Smuzhiyun 	.init_machine	= glantank_init_machine,
212*4882a593Smuzhiyun 	.restart	= iop3xx_restart,
213*4882a593Smuzhiyun MACHINE_END
214