1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/arm/mach-integrator/integrator_cp.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2003 Deep Blue Solutions Ltd
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/amba/mmci.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/irqchip.h>
11*4882a593Smuzhiyun #include <linux/of_irq.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/sched_clock.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <asm/mach/arch.h>
19*4882a593Smuzhiyun #include <asm/mach/map.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "hardware.h"
22*4882a593Smuzhiyun #include "cm.h"
23*4882a593Smuzhiyun #include "common.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Base address to the core module header */
26*4882a593Smuzhiyun static struct regmap *cm_map;
27*4882a593Smuzhiyun /* Base address to the CP controller */
28*4882a593Smuzhiyun static void __iomem *intcp_con_base;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define CM_COUNTER_OFFSET 0x28
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * Logical Physical
34*4882a593Smuzhiyun * f1400000 14000000 Interrupt controller
35*4882a593Smuzhiyun * f1600000 16000000 UART 0
36*4882a593Smuzhiyun * fca00000 ca000000 SIC
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
42*4882a593Smuzhiyun .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
43*4882a593Smuzhiyun .length = SZ_4K,
44*4882a593Smuzhiyun .type = MT_DEVICE
45*4882a593Smuzhiyun }, {
46*4882a593Smuzhiyun .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
47*4882a593Smuzhiyun .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
48*4882a593Smuzhiyun .length = SZ_4K,
49*4882a593Smuzhiyun .type = MT_DEVICE
50*4882a593Smuzhiyun }, {
51*4882a593Smuzhiyun .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
52*4882a593Smuzhiyun .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
53*4882a593Smuzhiyun .length = SZ_4K,
54*4882a593Smuzhiyun .type = MT_DEVICE
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
intcp_map_io(void)58*4882a593Smuzhiyun static void __init intcp_map_io(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * It seems that the card insertion interrupt remains active after
65*4882a593Smuzhiyun * we've acknowledged it. We therefore ignore the interrupt, and
66*4882a593Smuzhiyun * rely on reading it from the SIC. This also means that we must
67*4882a593Smuzhiyun * clear the latched interrupt.
68*4882a593Smuzhiyun */
mmc_status(struct device * dev)69*4882a593Smuzhiyun static unsigned int mmc_status(struct device *dev)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun unsigned int status = readl(__io_address(0xca000000 + 4));
72*4882a593Smuzhiyun writel(8, intcp_con_base + 8);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return status & 8;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static struct mmci_platform_data mmc_data = {
78*4882a593Smuzhiyun .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
79*4882a593Smuzhiyun .status = mmc_status,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
intcp_read_sched_clock(void)82*4882a593Smuzhiyun static u64 notrace intcp_read_sched_clock(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun unsigned int val;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* MMIO so discard return code */
87*4882a593Smuzhiyun regmap_read(cm_map, CM_COUNTER_OFFSET, &val);
88*4882a593Smuzhiyun return val;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
intcp_init_early(void)91*4882a593Smuzhiyun static void __init intcp_init_early(void)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun cm_map = syscon_regmap_lookup_by_compatible("arm,core-module-integrator");
94*4882a593Smuzhiyun if (IS_ERR(cm_map))
95*4882a593Smuzhiyun return;
96*4882a593Smuzhiyun sched_clock_register(intcp_read_sched_clock, 32, 24000000);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
intcp_init_irq_of(void)99*4882a593Smuzhiyun static void __init intcp_init_irq_of(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun cm_init();
102*4882a593Smuzhiyun irqchip_init();
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
107*4882a593Smuzhiyun * and enforce the bus names since these are used for clock lookups.
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
110*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
111*4882a593Smuzhiyun "mmci", &mmc_data),
112*4882a593Smuzhiyun { /* sentinel */ },
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun static const struct of_device_id intcp_syscon_match[] = {
116*4882a593Smuzhiyun { .compatible = "arm,integrator-cp-syscon"},
117*4882a593Smuzhiyun { },
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
intcp_init_of(void)120*4882a593Smuzhiyun static void __init intcp_init_of(void)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct device_node *cpcon;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun cpcon = of_find_matching_node(NULL, intcp_syscon_match);
125*4882a593Smuzhiyun if (!cpcon)
126*4882a593Smuzhiyun return;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun intcp_con_base = of_iomap(cpcon, 0);
129*4882a593Smuzhiyun if (!intcp_con_base)
130*4882a593Smuzhiyun return;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun of_platform_default_populate(NULL, intcp_auxdata_lookup, NULL);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static const char * intcp_dt_board_compat[] = {
136*4882a593Smuzhiyun "arm,integrator-cp",
137*4882a593Smuzhiyun NULL,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
141*4882a593Smuzhiyun .reserve = integrator_reserve,
142*4882a593Smuzhiyun .map_io = intcp_map_io,
143*4882a593Smuzhiyun .init_early = intcp_init_early,
144*4882a593Smuzhiyun .init_irq = intcp_init_irq_of,
145*4882a593Smuzhiyun .init_machine = intcp_init_of,
146*4882a593Smuzhiyun .dt_compat = intcp_dt_board_compat,
147*4882a593Smuzhiyun MACHINE_END
148