xref: /OK3568_Linux_fs/kernel/arch/arm/mach-integrator/integrator_ap.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  linux/arch/arm/mach-integrator/integrator_ap.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/syscore_ops.h>
10*4882a593Smuzhiyun #include <linux/amba/bus.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/irqchip.h>
13*4882a593Smuzhiyun #include <linux/of_irq.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/of_platform.h>
16*4882a593Smuzhiyun #include <linux/termios.h>
17*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <asm/mach/arch.h>
21*4882a593Smuzhiyun #include <asm/mach/map.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "hardware.h"
24*4882a593Smuzhiyun #include "cm.h"
25*4882a593Smuzhiyun #include "common.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* Regmap to the AP system controller */
28*4882a593Smuzhiyun static struct regmap *ap_syscon_map;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
32*4882a593Smuzhiyun  * is the (PA >> 12).
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  * Setup a VA for the Integrator interrupt controller (for header #0,
35*4882a593Smuzhiyun  * just for now).
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun #define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun  * Logical      Physical
41*4882a593Smuzhiyun  * f1400000	14000000	Interrupt controller
42*4882a593Smuzhiyun  * f1600000	16000000	UART 0
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
46*4882a593Smuzhiyun 	{
47*4882a593Smuzhiyun 		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
48*4882a593Smuzhiyun 		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
49*4882a593Smuzhiyun 		.length		= SZ_4K,
50*4882a593Smuzhiyun 		.type		= MT_DEVICE
51*4882a593Smuzhiyun 	}, {
52*4882a593Smuzhiyun 		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
53*4882a593Smuzhiyun 		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
54*4882a593Smuzhiyun 		.length		= SZ_4K,
55*4882a593Smuzhiyun 		.type		= MT_DEVICE
56*4882a593Smuzhiyun 	}
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
ap_map_io(void)59*4882a593Smuzhiyun static void __init ap_map_io(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #ifdef CONFIG_PM
65*4882a593Smuzhiyun static unsigned long ic_irq_enable;
66*4882a593Smuzhiyun 
irq_suspend(void)67*4882a593Smuzhiyun static int irq_suspend(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
70*4882a593Smuzhiyun 	return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
irq_resume(void)73*4882a593Smuzhiyun static void irq_resume(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	/* disable all irq sources */
76*4882a593Smuzhiyun 	cm_clear_irqs();
77*4882a593Smuzhiyun 	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
78*4882a593Smuzhiyun 	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun #else
83*4882a593Smuzhiyun #define irq_suspend NULL
84*4882a593Smuzhiyun #define irq_resume NULL
85*4882a593Smuzhiyun #endif
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun static struct syscore_ops irq_syscore_ops = {
88*4882a593Smuzhiyun 	.suspend	= irq_suspend,
89*4882a593Smuzhiyun 	.resume		= irq_resume,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
irq_syscore_init(void)92*4882a593Smuzhiyun static int __init irq_syscore_init(void)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	register_syscore_ops(&irq_syscore_ops);
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun device_initcall(irq_syscore_init);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun  * For the PL010 found in the Integrator/AP some of the UART control is
103*4882a593Smuzhiyun  * implemented in the system controller and accessed using a callback
104*4882a593Smuzhiyun  * from the driver.
105*4882a593Smuzhiyun  */
integrator_uart_set_mctrl(struct amba_device * dev,void __iomem * base,unsigned int mctrl)106*4882a593Smuzhiyun static void integrator_uart_set_mctrl(struct amba_device *dev,
107*4882a593Smuzhiyun 				void __iomem *base, unsigned int mctrl)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
110*4882a593Smuzhiyun 	u32 phybase = dev->res.start;
111*4882a593Smuzhiyun 	int ret;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	if (phybase == INTEGRATOR_UART0_BASE) {
114*4882a593Smuzhiyun 		/* UART0 */
115*4882a593Smuzhiyun 		rts_mask = 1 << 4;
116*4882a593Smuzhiyun 		dtr_mask = 1 << 5;
117*4882a593Smuzhiyun 	} else {
118*4882a593Smuzhiyun 		/* UART1 */
119*4882a593Smuzhiyun 		rts_mask = 1 << 6;
120*4882a593Smuzhiyun 		dtr_mask = 1 << 7;
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (mctrl & TIOCM_RTS)
124*4882a593Smuzhiyun 		ctrlc |= rts_mask;
125*4882a593Smuzhiyun 	else
126*4882a593Smuzhiyun 		ctrls |= rts_mask;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	if (mctrl & TIOCM_DTR)
129*4882a593Smuzhiyun 		ctrlc |= dtr_mask;
130*4882a593Smuzhiyun 	else
131*4882a593Smuzhiyun 		ctrls |= dtr_mask;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	ret = regmap_write(ap_syscon_map,
134*4882a593Smuzhiyun 			   INTEGRATOR_SC_CTRLS_OFFSET,
135*4882a593Smuzhiyun 			   ctrls);
136*4882a593Smuzhiyun 	if (ret)
137*4882a593Smuzhiyun 		pr_err("MODEM: unable to write PL010 UART CTRLS\n");
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	ret = regmap_write(ap_syscon_map,
140*4882a593Smuzhiyun 			   INTEGRATOR_SC_CTRLC_OFFSET,
141*4882a593Smuzhiyun 			   ctrlc);
142*4882a593Smuzhiyun 	if (ret)
143*4882a593Smuzhiyun 		pr_err("MODEM: unable to write PL010 UART CRTLC\n");
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun struct amba_pl010_data ap_uart_data = {
147*4882a593Smuzhiyun 	.set_mctrl = integrator_uart_set_mctrl,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
ap_init_early(void)150*4882a593Smuzhiyun void __init ap_init_early(void)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
ap_init_irq_of(void)154*4882a593Smuzhiyun static void __init ap_init_irq_of(void)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	cm_init();
157*4882a593Smuzhiyun 	irqchip_init();
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /* For the Device Tree, add in the UART callbacks as AUXDATA */
161*4882a593Smuzhiyun static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
162*4882a593Smuzhiyun 	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
163*4882a593Smuzhiyun 		"uart0", &ap_uart_data),
164*4882a593Smuzhiyun 	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
165*4882a593Smuzhiyun 		"uart1", &ap_uart_data),
166*4882a593Smuzhiyun 	{ /* sentinel */ },
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static const struct of_device_id ap_syscon_match[] = {
170*4882a593Smuzhiyun 	{ .compatible = "arm,integrator-ap-syscon"},
171*4882a593Smuzhiyun 	{ },
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
ap_init_of(void)174*4882a593Smuzhiyun static void __init ap_init_of(void)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	struct device_node *syscon;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	syscon = of_find_matching_node(NULL, ap_syscon_match);
181*4882a593Smuzhiyun 	if (!syscon)
182*4882a593Smuzhiyun 		return;
183*4882a593Smuzhiyun 	ap_syscon_map = syscon_node_to_regmap(syscon);
184*4882a593Smuzhiyun 	if (IS_ERR(ap_syscon_map)) {
185*4882a593Smuzhiyun 		pr_crit("could not find Integrator/AP system controller\n");
186*4882a593Smuzhiyun 		return;
187*4882a593Smuzhiyun 	}
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static const char * ap_dt_board_compat[] = {
191*4882a593Smuzhiyun 	"arm,integrator-ap",
192*4882a593Smuzhiyun 	NULL,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
196*4882a593Smuzhiyun 	.reserve	= integrator_reserve,
197*4882a593Smuzhiyun 	.map_io		= ap_map_io,
198*4882a593Smuzhiyun 	.init_early	= ap_init_early,
199*4882a593Smuzhiyun 	.init_irq	= ap_init_irq_of,
200*4882a593Smuzhiyun 	.init_machine	= ap_init_of,
201*4882a593Smuzhiyun 	.dt_compat      = ap_dt_board_compat,
202*4882a593Smuzhiyun MACHINE_END
203