1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * access the core module control register. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun u32 cm_get(void); 6*4882a593Smuzhiyun void cm_control(u32, u32); 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun struct device_node; 9*4882a593Smuzhiyun void cm_init(void); 10*4882a593Smuzhiyun void cm_clear_irqs(void); 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CM_CTRL_LED (1 << 0) 13*4882a593Smuzhiyun #define CM_CTRL_nMBDET (1 << 1) 14*4882a593Smuzhiyun #define CM_CTRL_REMAP (1 << 2) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Integrator/AP,PP2 specific 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define CM_CTRL_HIGHVECTORS (1 << 4) 20*4882a593Smuzhiyun #define CM_CTRL_BIGENDIAN (1 << 5) 21*4882a593Smuzhiyun #define CM_CTRL_FASTBUS (1 << 6) 22*4882a593Smuzhiyun #define CM_CTRL_SYNC (1 << 7) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * ARM926/946/966 Integrator/CP specific 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define CM_CTRL_LCDBIASEN (1 << 8) 28*4882a593Smuzhiyun #define CM_CTRL_LCDBIASUP (1 << 9) 29*4882a593Smuzhiyun #define CM_CTRL_LCDBIASDN (1 << 10) 30*4882a593Smuzhiyun #define CM_CTRL_LCDMUXSEL_MASK (7 << 11) 31*4882a593Smuzhiyun #define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) 32*4882a593Smuzhiyun #define CM_CTRL_LCDMUXSEL_VGA565_TFT555 (2 << 11) 33*4882a593Smuzhiyun #define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) 34*4882a593Smuzhiyun #define CM_CTRL_LCDMUXSEL_VGA555_TFT555 (4 << 11) 35*4882a593Smuzhiyun #define CM_CTRL_LCDEN0 (1 << 14) 36*4882a593Smuzhiyun #define CM_CTRL_LCDEN1 (1 << 15) 37*4882a593Smuzhiyun #define CM_CTRL_STATIC1 (1 << 16) 38*4882a593Smuzhiyun #define CM_CTRL_STATIC2 (1 << 17) 39*4882a593Smuzhiyun #define CM_CTRL_STATIC (1 << 18) 40*4882a593Smuzhiyun #define CM_CTRL_n24BITEN (1 << 19) 41*4882a593Smuzhiyun #define CM_CTRL_EBIWP (1 << 20) 42