1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun * Copyright 2011 Linaro Ltd.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/of_address.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/smp.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/cacheflush.h>
13*4882a593Smuzhiyun #include <asm/page.h>
14*4882a593Smuzhiyun #include <asm/smp_scu.h>
15*4882a593Smuzhiyun #include <asm/mach/map.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "common.h"
18*4882a593Smuzhiyun #include "hardware.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun u32 g_diag_reg;
21*4882a593Smuzhiyun static void __iomem *scu_base;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static struct map_desc scu_io_desc __initdata = {
24*4882a593Smuzhiyun /* .virtual and .pfn are run-time assigned */
25*4882a593Smuzhiyun .length = SZ_4K,
26*4882a593Smuzhiyun .type = MT_DEVICE,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
imx_scu_map_io(void)29*4882a593Smuzhiyun void __init imx_scu_map_io(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun unsigned long base;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Get SCU base */
34*4882a593Smuzhiyun asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun scu_io_desc.virtual = IMX_IO_P2V(base);
37*4882a593Smuzhiyun scu_io_desc.pfn = __phys_to_pfn(base);
38*4882a593Smuzhiyun iotable_init(&scu_io_desc, 1);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun scu_base = IMX_IO_ADDRESS(base);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
imx_boot_secondary(unsigned int cpu,struct task_struct * idle)43*4882a593Smuzhiyun static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun imx_set_cpu_jump(cpu, v7_secondary_startup);
46*4882a593Smuzhiyun imx_enable_cpu(cpu, true);
47*4882a593Smuzhiyun return 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * Initialise the CPU possible map early - this describes the CPUs
52*4882a593Smuzhiyun * which may be present or become present in the system.
53*4882a593Smuzhiyun */
imx_smp_init_cpus(void)54*4882a593Smuzhiyun static void __init imx_smp_init_cpus(void)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun int i, ncores;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun ncores = scu_get_core_count(scu_base);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (i = ncores; i < NR_CPUS; i++)
61*4882a593Smuzhiyun set_cpu_possible(i, false);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
imx_smp_prepare(void)64*4882a593Smuzhiyun void imx_smp_prepare(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun scu_enable(scu_base);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
imx_smp_prepare_cpus(unsigned int max_cpus)69*4882a593Smuzhiyun static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun imx_smp_prepare();
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * The diagnostic register holds the errata bits. Mostly bootloader
75*4882a593Smuzhiyun * does not bring up secondary cores, so that when errata bits are set
76*4882a593Smuzhiyun * in bootloader, they are set only for boot cpu. But on a SMP
77*4882a593Smuzhiyun * configuration, it should be equally done on every single core.
78*4882a593Smuzhiyun * Read the register from boot cpu here, and will replicate it into
79*4882a593Smuzhiyun * secondary cores when booting them.
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
82*4882a593Smuzhiyun sync_cache_w(&g_diag_reg);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun const struct smp_operations imx_smp_ops __initconst = {
86*4882a593Smuzhiyun .smp_init_cpus = imx_smp_init_cpus,
87*4882a593Smuzhiyun .smp_prepare_cpus = imx_smp_prepare_cpus,
88*4882a593Smuzhiyun .smp_boot_secondary = imx_boot_secondary,
89*4882a593Smuzhiyun #ifdef CONFIG_HOTPLUG_CPU
90*4882a593Smuzhiyun .cpu_die = imx_cpu_die,
91*4882a593Smuzhiyun .cpu_kill = imx_cpu_kill,
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #define DCFG_CCSR_SCRATCHRW1 0x200
96*4882a593Smuzhiyun
ls1021a_boot_secondary(unsigned int cpu,struct task_struct * idle)97*4882a593Smuzhiyun static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun arch_send_wakeup_ipi_mask(cpumask_of(cpu));
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
ls1021a_smp_prepare_cpus(unsigned int max_cpus)104*4882a593Smuzhiyun static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun struct device_node *np;
107*4882a593Smuzhiyun void __iomem *dcfg_base;
108*4882a593Smuzhiyun unsigned long paddr;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
111*4882a593Smuzhiyun dcfg_base = of_iomap(np, 0);
112*4882a593Smuzhiyun of_node_put(np);
113*4882a593Smuzhiyun BUG_ON(!dcfg_base);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun paddr = __pa_symbol(secondary_startup);
116*4882a593Smuzhiyun writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun iounmap(dcfg_base);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun const struct smp_operations ls1021a_smp_ops __initconst = {
122*4882a593Smuzhiyun .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
123*4882a593Smuzhiyun .smp_boot_secondary = ls1021a_boot_secondary,
124*4882a593Smuzhiyun };
125