1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARCH_MXC_H__ 8*4882a593Smuzhiyun #define __ASM_ARCH_MXC_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/types.h> 11*4882a593Smuzhiyun #include <soc/imx/cpu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __ASM_ARCH_MXC_HARDWARE_H__ 14*4882a593Smuzhiyun #error "Do not include directly." 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define IMX_DDR_TYPE_LPDDR2 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifdef CONFIG_SOC_IMX6SL cpu_is_imx6sl(void)22*4882a593Smuzhiyunstatic inline bool cpu_is_imx6sl(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6SL; 25*4882a593Smuzhiyun } 26*4882a593Smuzhiyun #else cpu_is_imx6sl(void)27*4882a593Smuzhiyunstatic inline bool cpu_is_imx6sl(void) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun return false; 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun cpu_is_imx6dl(void)33*4882a593Smuzhiyunstatic inline bool cpu_is_imx6dl(void) 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6DL; 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun cpu_is_imx6sx(void)38*4882a593Smuzhiyunstatic inline bool cpu_is_imx6sx(void) 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6SX; 41*4882a593Smuzhiyun } 42*4882a593Smuzhiyun cpu_is_imx6ul(void)43*4882a593Smuzhiyunstatic inline bool cpu_is_imx6ul(void) 44*4882a593Smuzhiyun { 45*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6UL; 46*4882a593Smuzhiyun } 47*4882a593Smuzhiyun cpu_is_imx6ull(void)48*4882a593Smuzhiyunstatic inline bool cpu_is_imx6ull(void) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6ULL; 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun cpu_is_imx6ulz(void)53*4882a593Smuzhiyunstatic inline bool cpu_is_imx6ulz(void) 54*4882a593Smuzhiyun { 55*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6ULZ; 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun cpu_is_imx6sll(void)58*4882a593Smuzhiyunstatic inline bool cpu_is_imx6sll(void) 59*4882a593Smuzhiyun { 60*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6SLL; 61*4882a593Smuzhiyun } 62*4882a593Smuzhiyun cpu_is_imx6q(void)63*4882a593Smuzhiyunstatic inline bool cpu_is_imx6q(void) 64*4882a593Smuzhiyun { 65*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX6Q; 66*4882a593Smuzhiyun } 67*4882a593Smuzhiyun cpu_is_imx7d(void)68*4882a593Smuzhiyunstatic inline bool cpu_is_imx7d(void) 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun return __mxc_cpu_type == MXC_CPU_IMX7D; 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct cpu_op { 74*4882a593Smuzhiyun u32 cpu_rate; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun int tzic_enable_wake(void); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun extern struct cpu_op *(*get_cpu_op)(int *op); 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define imx_readl readl_relaxed 83*4882a593Smuzhiyun #define imx_readw readw_relaxed 84*4882a593Smuzhiyun #define imx_writel writel_relaxed 85*4882a593Smuzhiyun #define imx_writew writew_relaxed 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* __ASM_ARCH_MXC_H__ */ 88