1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MACH_MX35_H__ 3*4882a593Smuzhiyun #define __MACH_MX35_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define MX35_AIPS1_BASE_ADDR 0x43f00000 6*4882a593Smuzhiyun #define MX35_AIPS1_SIZE SZ_1M 7*4882a593Smuzhiyun #define MX35_SPBA0_BASE_ADDR 0x50000000 8*4882a593Smuzhiyun #define MX35_SPBA0_SIZE SZ_1M 9*4882a593Smuzhiyun #define MX35_AIPS2_BASE_ADDR 0x53f00000 10*4882a593Smuzhiyun #define MX35_AIPS2_SIZE SZ_1M 11*4882a593Smuzhiyun #define MX35_AVIC_BASE_ADDR 0x68000000 12*4882a593Smuzhiyun #define MX35_AVIC_SIZE SZ_1M 13*4882a593Smuzhiyun #define MX35_X_MEMC_BASE_ADDR 0xb8000000 14*4882a593Smuzhiyun #define MX35_X_MEMC_SIZE SZ_64K 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MX35_IO_P2V(x) IMX_IO_P2V(x) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #endif /* ifndef __MACH_MX35_H__ */ 19