1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 1999,2000 Arm Limited
4*4882a593Smuzhiyun * Copyright (C) 2000 Deep Blue Solutions Ltd
5*4882a593Smuzhiyun * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6*4882a593Smuzhiyun * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7*4882a593Smuzhiyun * - add MX31 specific definitions
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/mm.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/pinctrl/machine.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/system_misc.h>
18*4882a593Smuzhiyun #include <asm/hardware/cache-l2x0.h>
19*4882a593Smuzhiyun #include <asm/mach/map.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "common.h"
22*4882a593Smuzhiyun #include "crmregs-imx3.h"
23*4882a593Smuzhiyun #include "hardware.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun void __iomem *mx3_ccm_base;
26*4882a593Smuzhiyun
imx3_idle(void)27*4882a593Smuzhiyun static void imx3_idle(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun unsigned long reg = 0;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun __asm__ __volatile__(
32*4882a593Smuzhiyun /* disable I and D cache */
33*4882a593Smuzhiyun "mrc p15, 0, %0, c1, c0, 0\n"
34*4882a593Smuzhiyun "bic %0, %0, #0x00001000\n"
35*4882a593Smuzhiyun "bic %0, %0, #0x00000004\n"
36*4882a593Smuzhiyun "mcr p15, 0, %0, c1, c0, 0\n"
37*4882a593Smuzhiyun /* invalidate I cache */
38*4882a593Smuzhiyun "mov %0, #0\n"
39*4882a593Smuzhiyun "mcr p15, 0, %0, c7, c5, 0\n"
40*4882a593Smuzhiyun /* clear and invalidate D cache */
41*4882a593Smuzhiyun "mov %0, #0\n"
42*4882a593Smuzhiyun "mcr p15, 0, %0, c7, c14, 0\n"
43*4882a593Smuzhiyun /* WFI */
44*4882a593Smuzhiyun "mov %0, #0\n"
45*4882a593Smuzhiyun "mcr p15, 0, %0, c7, c0, 4\n"
46*4882a593Smuzhiyun "nop\n" "nop\n" "nop\n" "nop\n"
47*4882a593Smuzhiyun "nop\n" "nop\n" "nop\n"
48*4882a593Smuzhiyun /* enable I and D cache */
49*4882a593Smuzhiyun "mrc p15, 0, %0, c1, c0, 0\n"
50*4882a593Smuzhiyun "orr %0, %0, #0x00001000\n"
51*4882a593Smuzhiyun "orr %0, %0, #0x00000004\n"
52*4882a593Smuzhiyun "mcr p15, 0, %0, c1, c0, 0\n"
53*4882a593Smuzhiyun : "=r" (reg));
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
imx3_ioremap_caller(phys_addr_t phys_addr,size_t size,unsigned int mtype,void * caller)56*4882a593Smuzhiyun static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
57*4882a593Smuzhiyun unsigned int mtype, void *caller)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun if (mtype == MT_DEVICE) {
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * Access all peripherals below 0x80000000 as nonshared device
62*4882a593Smuzhiyun * on mx3, but leave l2cc alone. Otherwise cache corruptions
63*4882a593Smuzhiyun * can occur.
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun if (phys_addr < 0x80000000 &&
66*4882a593Smuzhiyun !addr_in_module(phys_addr, MX3x_L2CC))
67*4882a593Smuzhiyun mtype = MT_DEVICE_NONSHARED;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return __arm_ioremap_caller(phys_addr, size, mtype, caller);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #ifdef CONFIG_SOC_IMX31
74*4882a593Smuzhiyun static struct map_desc mx31_io_desc[] __initdata = {
75*4882a593Smuzhiyun imx_map_entry(MX31, X_MEMC, MT_DEVICE),
76*4882a593Smuzhiyun imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
77*4882a593Smuzhiyun imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
78*4882a593Smuzhiyun imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
79*4882a593Smuzhiyun imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * This function initializes the memory map. It is called during the
84*4882a593Smuzhiyun * system startup to create static physical to virtual memory mappings
85*4882a593Smuzhiyun * for the IO modules.
86*4882a593Smuzhiyun */
mx31_map_io(void)87*4882a593Smuzhiyun void __init mx31_map_io(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
imx31_idle(void)92*4882a593Smuzhiyun static void imx31_idle(void)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
95*4882a593Smuzhiyun reg &= ~MXC_CCM_CCMR_LPM_MASK;
96*4882a593Smuzhiyun imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun imx3_idle();
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
imx31_init_early(void)101*4882a593Smuzhiyun void __init imx31_init_early(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct device_node *np;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun mxc_set_cpu_type(MXC_CPU_MX31);
106*4882a593Smuzhiyun arch_ioremap_caller = imx3_ioremap_caller;
107*4882a593Smuzhiyun arm_pm_idle = imx31_idle;
108*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
109*4882a593Smuzhiyun mx3_ccm_base = of_iomap(np, 0);
110*4882a593Smuzhiyun BUG_ON(!mx3_ccm_base);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
mx31_init_irq(void)113*4882a593Smuzhiyun void __init mx31_init_irq(void)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun void __iomem *avic_base;
116*4882a593Smuzhiyun struct device_node *np;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx31-avic");
119*4882a593Smuzhiyun avic_base = of_iomap(np, 0);
120*4882a593Smuzhiyun BUG_ON(!avic_base);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun mxc_init_irq(avic_base);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun #endif /* ifdef CONFIG_SOC_IMX31 */
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #ifdef CONFIG_SOC_IMX35
127*4882a593Smuzhiyun static struct map_desc mx35_io_desc[] __initdata = {
128*4882a593Smuzhiyun imx_map_entry(MX35, X_MEMC, MT_DEVICE),
129*4882a593Smuzhiyun imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
130*4882a593Smuzhiyun imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
131*4882a593Smuzhiyun imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
132*4882a593Smuzhiyun imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
mx35_map_io(void)135*4882a593Smuzhiyun void __init mx35_map_io(void)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
imx35_idle(void)140*4882a593Smuzhiyun static void imx35_idle(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
143*4882a593Smuzhiyun reg &= ~MXC_CCM_CCMR_LPM_MASK;
144*4882a593Smuzhiyun reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
145*4882a593Smuzhiyun imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun imx3_idle();
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
imx35_init_early(void)150*4882a593Smuzhiyun void __init imx35_init_early(void)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct device_node *np;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun mxc_set_cpu_type(MXC_CPU_MX35);
155*4882a593Smuzhiyun arm_pm_idle = imx35_idle;
156*4882a593Smuzhiyun arch_ioremap_caller = imx3_ioremap_caller;
157*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm");
158*4882a593Smuzhiyun mx3_ccm_base = of_iomap(np, 0);
159*4882a593Smuzhiyun BUG_ON(!mx3_ccm_base);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
mx35_init_irq(void)162*4882a593Smuzhiyun void __init mx35_init_irq(void)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun void __iomem *avic_base;
165*4882a593Smuzhiyun struct device_node *np;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx35-avic");
168*4882a593Smuzhiyun avic_base = of_iomap(np, 0);
169*4882a593Smuzhiyun BUG_ON(!avic_base);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun mxc_init_irq(avic_base);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun #endif /* ifdef CONFIG_SOC_IMX35 */
174