1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <linux/irqchip.h>
6*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
7*4882a593Smuzhiyun #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8*4882a593Smuzhiyun #include <linux/micrel_phy.h>
9*4882a593Smuzhiyun #include <linux/of_platform.h>
10*4882a593Smuzhiyun #include <linux/phy.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun #include <asm/mach/arch.h>
13*4882a593Smuzhiyun #include <asm/mach/map.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "common.h"
16*4882a593Smuzhiyun #include "cpuidle.h"
17*4882a593Smuzhiyun
imx6ul_enet_clk_init(void)18*4882a593Smuzhiyun static void __init imx6ul_enet_clk_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct regmap *gpr;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
23*4882a593Smuzhiyun if (!IS_ERR(gpr))
24*4882a593Smuzhiyun regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
25*4882a593Smuzhiyun IMX6UL_GPR1_ENET_CLK_OUTPUT);
26*4882a593Smuzhiyun else
27*4882a593Smuzhiyun pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
ksz8081_phy_fixup(struct phy_device * dev)30*4882a593Smuzhiyun static int ksz8081_phy_fixup(struct phy_device *dev)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
33*4882a593Smuzhiyun phy_write(dev, 0x1f, 0x8110);
34*4882a593Smuzhiyun phy_write(dev, 0x16, 0x201);
35*4882a593Smuzhiyun } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
36*4882a593Smuzhiyun phy_write(dev, 0x1f, 0x8190);
37*4882a593Smuzhiyun phy_write(dev, 0x16, 0x202);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
imx6ul_enet_phy_init(void)43*4882a593Smuzhiyun static void __init imx6ul_enet_phy_init(void)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun if (IS_BUILTIN(CONFIG_PHYLIB))
46*4882a593Smuzhiyun phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
47*4882a593Smuzhiyun ksz8081_phy_fixup);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
imx6ul_enet_init(void)50*4882a593Smuzhiyun static inline void imx6ul_enet_init(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun imx6ul_enet_clk_init();
53*4882a593Smuzhiyun imx6ul_enet_phy_init();
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
imx6ul_init_machine(void)56*4882a593Smuzhiyun static void __init imx6ul_init_machine(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun of_platform_default_populate(NULL, NULL, NULL);
59*4882a593Smuzhiyun imx6ul_enet_init();
60*4882a593Smuzhiyun imx_anatop_init();
61*4882a593Smuzhiyun imx6ul_pm_init();
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
imx6ul_init_irq(void)64*4882a593Smuzhiyun static void __init imx6ul_init_irq(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun imx_init_revision_from_anatop();
67*4882a593Smuzhiyun imx_src_init();
68*4882a593Smuzhiyun irqchip_init();
69*4882a593Smuzhiyun imx6_pm_ccm_init("fsl,imx6ul-ccm");
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
imx6ul_init_late(void)72*4882a593Smuzhiyun static void __init imx6ul_init_late(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun imx6sx_cpuidle_init();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
77*4882a593Smuzhiyun platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const char * const imx6ul_dt_compat[] __initconst = {
81*4882a593Smuzhiyun "fsl,imx6ul",
82*4882a593Smuzhiyun "fsl,imx6ull",
83*4882a593Smuzhiyun NULL,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
87*4882a593Smuzhiyun .init_irq = imx6ul_init_irq,
88*4882a593Smuzhiyun .init_machine = imx6ul_init_machine,
89*4882a593Smuzhiyun .init_late = imx6ul_init_late,
90*4882a593Smuzhiyun .dt_compat = imx6ul_dt_compat,
91*4882a593Smuzhiyun MACHINE_END
92