1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4*4882a593Smuzhiyun * Copyright 2011 Linaro Ltd.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/irq.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/of_irq.h>
11*4882a593Smuzhiyun #include <linux/of_platform.h>
12*4882a593Smuzhiyun #include <asm/mach/arch.h>
13*4882a593Smuzhiyun #include <asm/mach/time.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "common.h"
16*4882a593Smuzhiyun #include "hardware.h"
17*4882a593Smuzhiyun
imx51_init_early(void)18*4882a593Smuzhiyun static void __init imx51_init_early(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun mxc_set_cpu_type(MXC_CPU_MX51);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
25*4882a593Smuzhiyun * the Freescale marketing division. However this did not remove the
26*4882a593Smuzhiyun * hardware from the chip which still needs to be configured for proper
27*4882a593Smuzhiyun * IPU support.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun #define MX51_MIPI_HSC_BASE 0x83fdc000
imx51_ipu_mipi_setup(void)30*4882a593Smuzhiyun static void __init imx51_ipu_mipi_setup(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun void __iomem *hsc_addr;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
35*4882a593Smuzhiyun WARN_ON(!hsc_addr);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* setup MIPI module to legacy mode */
38*4882a593Smuzhiyun imx_writel(0xf00, hsc_addr);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
41*4882a593Smuzhiyun imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun iounmap(hsc_addr);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
imx51_m4if_setup(void)46*4882a593Smuzhiyun static void __init imx51_m4if_setup(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun void __iomem *m4if_base;
49*4882a593Smuzhiyun struct device_node *np;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if");
52*4882a593Smuzhiyun if (!np)
53*4882a593Smuzhiyun return;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun m4if_base = of_iomap(np, 0);
56*4882a593Smuzhiyun of_node_put(np);
57*4882a593Smuzhiyun if (!m4if_base) {
58*4882a593Smuzhiyun pr_err("Unable to map M4IF registers\n");
59*4882a593Smuzhiyun return;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * Configure VPU and IPU with higher priorities
64*4882a593Smuzhiyun * in order to avoid artifacts during video playback
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun writel_relaxed(0x00000203, m4if_base + 0x40);
67*4882a593Smuzhiyun writel_relaxed(0x00000000, m4if_base + 0x44);
68*4882a593Smuzhiyun writel_relaxed(0x00120125, m4if_base + 0x9c);
69*4882a593Smuzhiyun writel_relaxed(0x001901A3, m4if_base + 0x48);
70*4882a593Smuzhiyun iounmap(m4if_base);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
imx51_dt_init(void)73*4882a593Smuzhiyun static void __init imx51_dt_init(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun imx51_ipu_mipi_setup();
76*4882a593Smuzhiyun imx_src_init();
77*4882a593Smuzhiyun imx51_m4if_setup();
78*4882a593Smuzhiyun imx5_pmu_init();
79*4882a593Smuzhiyun imx_aips_allow_unprivileged_access("fsl,imx51-aipstz");
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
imx51_init_late(void)82*4882a593Smuzhiyun static void __init imx51_init_late(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun mx51_neon_fixup();
85*4882a593Smuzhiyun imx51_pm_init();
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const char * const imx51_dt_board_compat[] __initconst = {
89*4882a593Smuzhiyun "fsl,imx51",
90*4882a593Smuzhiyun NULL
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
94*4882a593Smuzhiyun .init_early = imx51_init_early,
95*4882a593Smuzhiyun .init_machine = imx51_dt_init,
96*4882a593Smuzhiyun .init_late = imx51_init_late,
97*4882a593Smuzhiyun .dt_compat = imx51_dt_board_compat,
98*4882a593Smuzhiyun MACHINE_END
99