1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4*4882a593Smuzhiyun * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARCH_MXC_IIM_H__ 8*4882a593Smuzhiyun #define __ASM_ARCH_MXC_IIM_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Register offsets */ 11*4882a593Smuzhiyun #define MXC_IIMSTAT 0x0000 12*4882a593Smuzhiyun #define MXC_IIMSTATM 0x0004 13*4882a593Smuzhiyun #define MXC_IIMERR 0x0008 14*4882a593Smuzhiyun #define MXC_IIMEMASK 0x000C 15*4882a593Smuzhiyun #define MXC_IIMFCTL 0x0010 16*4882a593Smuzhiyun #define MXC_IIMUA 0x0014 17*4882a593Smuzhiyun #define MXC_IIMLA 0x0018 18*4882a593Smuzhiyun #define MXC_IIMSDAT 0x001C 19*4882a593Smuzhiyun #define MXC_IIMPREV 0x0020 20*4882a593Smuzhiyun #define MXC_IIMSREV 0x0024 21*4882a593Smuzhiyun #define MXC_IIMPRG_P 0x0028 22*4882a593Smuzhiyun #define MXC_IIMSCS0 0x002C 23*4882a593Smuzhiyun #define MXC_IIMSCS1 0x0030 24*4882a593Smuzhiyun #define MXC_IIMSCS2 0x0034 25*4882a593Smuzhiyun #define MXC_IIMSCS3 0x0038 26*4882a593Smuzhiyun #define MXC_IIMFBAC0 0x0800 27*4882a593Smuzhiyun #define MXC_IIMJAC 0x0804 28*4882a593Smuzhiyun #define MXC_IIMHWV1 0x0808 29*4882a593Smuzhiyun #define MXC_IIMHWV2 0x080C 30*4882a593Smuzhiyun #define MXC_IIMHAB0 0x0810 31*4882a593Smuzhiyun #define MXC_IIMHAB1 0x0814 32*4882a593Smuzhiyun /* Definitions for i.MX27 TO2 */ 33*4882a593Smuzhiyun #define MXC_IIMMAC 0x0814 34*4882a593Smuzhiyun #define MXC_IIMPREV_FUSE 0x0818 35*4882a593Smuzhiyun #define MXC_IIMSREV_FUSE 0x081C 36*4882a593Smuzhiyun #define MXC_IIMSJC_CHALL_0 0x0820 37*4882a593Smuzhiyun #define MXC_IIMSJC_CHALL_7 0x083C 38*4882a593Smuzhiyun #define MXC_IIMFB0UC17 0x0840 39*4882a593Smuzhiyun #define MXC_IIMFB0UC255 0x0BFC 40*4882a593Smuzhiyun #define MXC_IIMFBAC1 0x0C00 41*4882a593Smuzhiyun /* Definitions for i.MX27 TO2 */ 42*4882a593Smuzhiyun #define MXC_IIMSUID 0x0C04 43*4882a593Smuzhiyun #define MXC_IIMKEY0 0x0C04 44*4882a593Smuzhiyun #define MXC_IIMKEY20 0x0C54 45*4882a593Smuzhiyun #define MXC_IIMSJC_RESP_0 0x0C58 46*4882a593Smuzhiyun #define MXC_IIMSJC_RESP_7 0x0C74 47*4882a593Smuzhiyun #define MXC_IIMFB1UC30 0x0C78 48*4882a593Smuzhiyun #define MXC_IIMFB1UC255 0x0FFC 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Bit definitions */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MXC_IIMHWV1_WLOCK (0x1 << 7) 53*4882a593Smuzhiyun #define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6) 54*4882a593Smuzhiyun #define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5) 55*4882a593Smuzhiyun #define MXC_IIMHWV1_BOOT_INT (0x1 << 4) 56*4882a593Smuzhiyun #define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3) 57*4882a593Smuzhiyun #define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2) 58*4882a593Smuzhiyun #define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define MXC_IIMHWV2_WLOCK (0x1 << 7) 61*4882a593Smuzhiyun #define MXC_IIMHWV2_BP_SDMA (0x1 << 6) 62*4882a593Smuzhiyun #define MXC_IIMHWV2_SCM_DCM (0x1 << 5) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __ASM_ARCH_MXC_IIM_H__ */ 65