1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun * Copyright 2017-2018 NXP
5*4882a593Smuzhiyun * Anson Huang <Anson.Huang@nxp.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/cpuidle.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <asm/cpuidle.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "common.h"
13*4882a593Smuzhiyun #include "cpuidle.h"
14*4882a593Smuzhiyun
imx7ulp_enter_wait(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)15*4882a593Smuzhiyun static int imx7ulp_enter_wait(struct cpuidle_device *dev,
16*4882a593Smuzhiyun struct cpuidle_driver *drv, int index)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun if (index == 1)
19*4882a593Smuzhiyun imx7ulp_set_lpm(ULP_PM_WAIT);
20*4882a593Smuzhiyun else
21*4882a593Smuzhiyun imx7ulp_set_lpm(ULP_PM_STOP);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun cpu_do_idle();
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun imx7ulp_set_lpm(ULP_PM_RUN);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun return index;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static struct cpuidle_driver imx7ulp_cpuidle_driver = {
31*4882a593Smuzhiyun .name = "imx7ulp_cpuidle",
32*4882a593Smuzhiyun .owner = THIS_MODULE,
33*4882a593Smuzhiyun .states = {
34*4882a593Smuzhiyun /* WFI */
35*4882a593Smuzhiyun ARM_CPUIDLE_WFI_STATE,
36*4882a593Smuzhiyun /* WAIT */
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun .exit_latency = 50,
39*4882a593Smuzhiyun .target_residency = 75,
40*4882a593Smuzhiyun .enter = imx7ulp_enter_wait,
41*4882a593Smuzhiyun .name = "WAIT",
42*4882a593Smuzhiyun .desc = "PSTOP2",
43*4882a593Smuzhiyun },
44*4882a593Smuzhiyun /* STOP */
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun .exit_latency = 100,
47*4882a593Smuzhiyun .target_residency = 150,
48*4882a593Smuzhiyun .enter = imx7ulp_enter_wait,
49*4882a593Smuzhiyun .name = "STOP",
50*4882a593Smuzhiyun .desc = "PSTOP1",
51*4882a593Smuzhiyun },
52*4882a593Smuzhiyun },
53*4882a593Smuzhiyun .state_count = 3,
54*4882a593Smuzhiyun .safe_state_index = 0,
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
imx7ulp_cpuidle_init(void)57*4882a593Smuzhiyun int __init imx7ulp_cpuidle_init(void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun return cpuidle_register(&imx7ulp_cpuidle_driver, NULL);
60*4882a593Smuzhiyun }
61