1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This file contains the CPU initialization code.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/types.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "hardware.h"
17*4882a593Smuzhiyun #include "common.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static int mx5_cpu_rev = -1;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define IIM_SREV 0x24
22*4882a593Smuzhiyun
imx5_read_srev_reg(const char * compat)23*4882a593Smuzhiyun static u32 imx5_read_srev_reg(const char *compat)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun void __iomem *iim_base;
26*4882a593Smuzhiyun struct device_node *np;
27*4882a593Smuzhiyun u32 srev;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, compat);
30*4882a593Smuzhiyun iim_base = of_iomap(np, 0);
31*4882a593Smuzhiyun WARN_ON(!iim_base);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun srev = readl(iim_base + IIM_SREV) & 0xff;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun iounmap(iim_base);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return srev;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
get_mx51_srev(void)40*4882a593Smuzhiyun static int get_mx51_srev(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun switch (rev) {
45*4882a593Smuzhiyun case 0x0:
46*4882a593Smuzhiyun return IMX_CHIP_REVISION_2_0;
47*4882a593Smuzhiyun case 0x10:
48*4882a593Smuzhiyun return IMX_CHIP_REVISION_3_0;
49*4882a593Smuzhiyun default:
50*4882a593Smuzhiyun return IMX_CHIP_REVISION_UNKNOWN;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * Returns:
56*4882a593Smuzhiyun * the silicon revision of the cpu
57*4882a593Smuzhiyun */
mx51_revision(void)58*4882a593Smuzhiyun int mx51_revision(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun if (mx5_cpu_rev == -1)
61*4882a593Smuzhiyun mx5_cpu_rev = get_mx51_srev();
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return mx5_cpu_rev;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun EXPORT_SYMBOL(mx51_revision);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #ifdef CONFIG_NEON
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * All versions of the silicon before Rev. 3 have broken NEON implementations.
71*4882a593Smuzhiyun * Dependent on link order - so the assumption is that vfp_init is called
72*4882a593Smuzhiyun * before us.
73*4882a593Smuzhiyun */
mx51_neon_fixup(void)74*4882a593Smuzhiyun int __init mx51_neon_fixup(void)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
77*4882a593Smuzhiyun (elf_hwcap & HWCAP_NEON)) {
78*4882a593Smuzhiyun elf_hwcap &= ~HWCAP_NEON;
79*4882a593Smuzhiyun pr_info("Turning off NEON support, detected broken NEON implementation\n");
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #endif
85*4882a593Smuzhiyun
get_mx53_srev(void)86*4882a593Smuzhiyun static int get_mx53_srev(void)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun switch (rev) {
91*4882a593Smuzhiyun case 0x0:
92*4882a593Smuzhiyun return IMX_CHIP_REVISION_1_0;
93*4882a593Smuzhiyun case 0x2:
94*4882a593Smuzhiyun return IMX_CHIP_REVISION_2_0;
95*4882a593Smuzhiyun case 0x3:
96*4882a593Smuzhiyun return IMX_CHIP_REVISION_2_1;
97*4882a593Smuzhiyun default:
98*4882a593Smuzhiyun return IMX_CHIP_REVISION_UNKNOWN;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * Returns:
104*4882a593Smuzhiyun * the silicon revision of the cpu
105*4882a593Smuzhiyun */
mx53_revision(void)106*4882a593Smuzhiyun int mx53_revision(void)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun if (mx5_cpu_rev == -1)
109*4882a593Smuzhiyun mx5_cpu_rev = get_mx53_srev();
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return mx5_cpu_rev;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun EXPORT_SYMBOL(mx53_revision);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #define ARM_GPC 0x4
116*4882a593Smuzhiyun #define DBGEN BIT(16)
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /*
119*4882a593Smuzhiyun * This enables the DBGEN bit in ARM_GPC register, which is
120*4882a593Smuzhiyun * required for accessing some performance counter features.
121*4882a593Smuzhiyun * Technically it is only required while perf is used, but to
122*4882a593Smuzhiyun * keep the source code simple we just enable it all the time
123*4882a593Smuzhiyun * when the kernel configuration allows using the feature.
124*4882a593Smuzhiyun */
imx5_pmu_init(void)125*4882a593Smuzhiyun void __init imx5_pmu_init(void)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun void __iomem *tigerp_base;
128*4882a593Smuzhiyun struct device_node *np;
129*4882a593Smuzhiyun u32 gpc;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_ARM_PMU))
132*4882a593Smuzhiyun return;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
135*4882a593Smuzhiyun if (!np)
136*4882a593Smuzhiyun return;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (!of_property_read_bool(np, "secure-reg-access"))
139*4882a593Smuzhiyun goto exit;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun of_node_put(np);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp");
144*4882a593Smuzhiyun if (!np)
145*4882a593Smuzhiyun return;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun tigerp_base = of_iomap(np, 0);
148*4882a593Smuzhiyun if (!tigerp_base)
149*4882a593Smuzhiyun goto exit;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun gpc = readl_relaxed(tigerp_base + ARM_GPC);
152*4882a593Smuzhiyun gpc |= DBGEN;
153*4882a593Smuzhiyun writel_relaxed(gpc, tigerp_base + ARM_GPC);
154*4882a593Smuzhiyun iounmap(tigerp_base);
155*4882a593Smuzhiyun exit:
156*4882a593Smuzhiyun of_node_put(np);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun }
159