1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * MX35 CPU type detection 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #include <linux/module.h> 8*4882a593Smuzhiyun #include <linux/of_address.h> 9*4882a593Smuzhiyun #include <linux/io.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "hardware.h" 12*4882a593Smuzhiyun #include "iim.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun static int mx35_cpu_rev = -1; 15*4882a593Smuzhiyun mx35_read_cpu_rev(void)16*4882a593Smuzhiyunstatic int mx35_read_cpu_rev(void) 17*4882a593Smuzhiyun { 18*4882a593Smuzhiyun void __iomem *iim_base; 19*4882a593Smuzhiyun struct device_node *np; 20*4882a593Smuzhiyun u32 rev; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim"); 23*4882a593Smuzhiyun iim_base = of_iomap(np, 0); 24*4882a593Smuzhiyun BUG_ON(!iim_base); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun rev = imx_readl(iim_base + MXC_IIMSREV); 27*4882a593Smuzhiyun switch (rev) { 28*4882a593Smuzhiyun case 0x00: 29*4882a593Smuzhiyun return IMX_CHIP_REVISION_1_0; 30*4882a593Smuzhiyun case 0x10: 31*4882a593Smuzhiyun return IMX_CHIP_REVISION_2_0; 32*4882a593Smuzhiyun case 0x11: 33*4882a593Smuzhiyun return IMX_CHIP_REVISION_2_1; 34*4882a593Smuzhiyun default: 35*4882a593Smuzhiyun return IMX_CHIP_REVISION_UNKNOWN; 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun mx35_revision(void)39*4882a593Smuzhiyunint mx35_revision(void) 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun if (mx35_cpu_rev == -1) 42*4882a593Smuzhiyun mx35_cpu_rev = mx35_read_cpu_rev(); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun return mx35_cpu_rev; 45*4882a593Smuzhiyun } 46*4882a593Smuzhiyun EXPORT_SYMBOL(mx35_revision); 47