1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __ASM_ARCH_MXC_COMMON_H__
8*4882a593Smuzhiyun #define __ASM_ARCH_MXC_COMMON_H__
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/reboot.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct irq_data;
13*4882a593Smuzhiyun struct platform_device;
14*4882a593Smuzhiyun struct pt_regs;
15*4882a593Smuzhiyun struct clk;
16*4882a593Smuzhiyun struct device_node;
17*4882a593Smuzhiyun enum mxc_cpu_pwr_mode;
18*4882a593Smuzhiyun struct of_device_id;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun void mx31_map_io(void);
21*4882a593Smuzhiyun void mx35_map_io(void);
22*4882a593Smuzhiyun void imx21_init_early(void);
23*4882a593Smuzhiyun void imx31_init_early(void);
24*4882a593Smuzhiyun void imx35_init_early(void);
25*4882a593Smuzhiyun void mxc_init_irq(void __iomem *);
26*4882a593Smuzhiyun void mx31_init_irq(void);
27*4882a593Smuzhiyun void mx35_init_irq(void);
28*4882a593Smuzhiyun void mxc_set_cpu_type(unsigned int type);
29*4882a593Smuzhiyun void mxc_restart(enum reboot_mode, const char *);
30*4882a593Smuzhiyun void mxc_arch_reset_init(void __iomem *);
31*4882a593Smuzhiyun void imx1_reset_init(void __iomem *);
32*4882a593Smuzhiyun void imx_set_aips(void __iomem *);
33*4882a593Smuzhiyun void imx_aips_allow_unprivileged_access(const char *compat);
34*4882a593Smuzhiyun int mxc_device_init(void);
35*4882a593Smuzhiyun void imx_set_soc_revision(unsigned int rev);
36*4882a593Smuzhiyun void imx_init_revision_from_anatop(void);
37*4882a593Smuzhiyun void imx6_enable_rbc(bool enable);
38*4882a593Smuzhiyun void imx_gpc_check_dt(void);
39*4882a593Smuzhiyun void imx_gpc_set_arm_power_in_lpm(bool power_off);
40*4882a593Smuzhiyun void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);
41*4882a593Smuzhiyun void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
42*4882a593Smuzhiyun void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
43*4882a593Smuzhiyun void imx25_pm_init(void);
44*4882a593Smuzhiyun void imx27_pm_init(void);
45*4882a593Smuzhiyun void imx5_pmu_init(void);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun enum mxc_cpu_pwr_mode {
48*4882a593Smuzhiyun WAIT_CLOCKED, /* wfi only */
49*4882a593Smuzhiyun WAIT_UNCLOCKED, /* WAIT */
50*4882a593Smuzhiyun WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
51*4882a593Smuzhiyun STOP_POWER_ON, /* just STOP */
52*4882a593Smuzhiyun STOP_POWER_OFF, /* STOP + SRPG */
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun enum ulp_cpu_pwr_mode {
56*4882a593Smuzhiyun ULP_PM_HSRUN, /* High speed run mode */
57*4882a593Smuzhiyun ULP_PM_RUN, /* Run mode */
58*4882a593Smuzhiyun ULP_PM_WAIT, /* Wait mode */
59*4882a593Smuzhiyun ULP_PM_STOP, /* Stop mode */
60*4882a593Smuzhiyun ULP_PM_VLPS, /* Very low power stop mode */
61*4882a593Smuzhiyun ULP_PM_VLLS, /* very low leakage stop mode */
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun void imx_enable_cpu(int cpu, bool enable);
65*4882a593Smuzhiyun void imx_set_cpu_jump(int cpu, void *jump_addr);
66*4882a593Smuzhiyun u32 imx_get_cpu_arg(int cpu);
67*4882a593Smuzhiyun void imx_set_cpu_arg(int cpu, u32 arg);
68*4882a593Smuzhiyun #ifdef CONFIG_SMP
69*4882a593Smuzhiyun void v7_secondary_startup(void);
70*4882a593Smuzhiyun void imx_scu_map_io(void);
71*4882a593Smuzhiyun void imx_smp_prepare(void);
72*4882a593Smuzhiyun #else
imx_scu_map_io(void)73*4882a593Smuzhiyun static inline void imx_scu_map_io(void) {}
imx_smp_prepare(void)74*4882a593Smuzhiyun static inline void imx_smp_prepare(void) {}
75*4882a593Smuzhiyun #endif
76*4882a593Smuzhiyun void imx_src_init(void);
77*4882a593Smuzhiyun void imx_gpc_pre_suspend(bool arm_power_off);
78*4882a593Smuzhiyun void imx_gpc_post_resume(void);
79*4882a593Smuzhiyun void imx_gpc_mask_all(void);
80*4882a593Smuzhiyun void imx_gpc_restore_all(void);
81*4882a593Smuzhiyun void imx_gpc_hwirq_mask(unsigned int hwirq);
82*4882a593Smuzhiyun void imx_gpc_hwirq_unmask(unsigned int hwirq);
83*4882a593Smuzhiyun void imx_anatop_init(void);
84*4882a593Smuzhiyun void imx_anatop_pre_suspend(void);
85*4882a593Smuzhiyun void imx_anatop_post_resume(void);
86*4882a593Smuzhiyun int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
87*4882a593Smuzhiyun void imx6_set_int_mem_clk_lpm(bool enable);
88*4882a593Smuzhiyun void imx6sl_set_wait_clk(bool enter);
89*4882a593Smuzhiyun int imx_mmdc_get_ddr_type(void);
90*4882a593Smuzhiyun int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun void imx_cpu_die(unsigned int cpu);
93*4882a593Smuzhiyun int imx_cpu_kill(unsigned int cpu);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #ifdef CONFIG_SUSPEND
96*4882a593Smuzhiyun void imx53_suspend(void __iomem *ocram_vbase);
97*4882a593Smuzhiyun extern const u32 imx53_suspend_sz;
98*4882a593Smuzhiyun void imx6_suspend(void __iomem *ocram_vbase);
99*4882a593Smuzhiyun #else
imx53_suspend(void __iomem * ocram_vbase)100*4882a593Smuzhiyun static inline void imx53_suspend(void __iomem *ocram_vbase) {}
101*4882a593Smuzhiyun static const u32 imx53_suspend_sz;
imx6_suspend(void __iomem * ocram_vbase)102*4882a593Smuzhiyun static inline void imx6_suspend(void __iomem *ocram_vbase) {}
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun void v7_cpu_resume(void);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun void imx6_pm_ccm_init(const char *ccm_compat);
108*4882a593Smuzhiyun void imx6q_pm_init(void);
109*4882a593Smuzhiyun void imx6dl_pm_init(void);
110*4882a593Smuzhiyun void imx6sl_pm_init(void);
111*4882a593Smuzhiyun void imx6sx_pm_init(void);
112*4882a593Smuzhiyun void imx6ul_pm_init(void);
113*4882a593Smuzhiyun void imx7ulp_pm_init(void);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #ifdef CONFIG_PM
116*4882a593Smuzhiyun void imx51_pm_init(void);
117*4882a593Smuzhiyun void imx53_pm_init(void);
118*4882a593Smuzhiyun #else
imx51_pm_init(void)119*4882a593Smuzhiyun static inline void imx51_pm_init(void) {}
imx53_pm_init(void)120*4882a593Smuzhiyun static inline void imx53_pm_init(void) {}
121*4882a593Smuzhiyun #endif
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #ifdef CONFIG_NEON
124*4882a593Smuzhiyun int mx51_neon_fixup(void);
125*4882a593Smuzhiyun #else
mx51_neon_fixup(void)126*4882a593Smuzhiyun static inline int mx51_neon_fixup(void) { return 0; }
127*4882a593Smuzhiyun #endif
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #ifdef CONFIG_CACHE_L2X0
130*4882a593Smuzhiyun void imx_init_l2cache(void);
131*4882a593Smuzhiyun #else
imx_init_l2cache(void)132*4882a593Smuzhiyun static inline void imx_init_l2cache(void) {}
133*4882a593Smuzhiyun #endif
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun extern const struct smp_operations imx_smp_ops;
136*4882a593Smuzhiyun extern const struct smp_operations ls1021a_smp_ops;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun #endif
139