1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2012 Samsung Electronics. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Exynos - SMC Call 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_EXYNOS_SMC_H 9*4882a593Smuzhiyun #define __ASM_ARCH_EXYNOS_SMC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SMC_CMD_INIT (-1) 12*4882a593Smuzhiyun #define SMC_CMD_INFO (-2) 13*4882a593Smuzhiyun /* For Power Management */ 14*4882a593Smuzhiyun #define SMC_CMD_SLEEP (-3) 15*4882a593Smuzhiyun #define SMC_CMD_CPU1BOOT (-4) 16*4882a593Smuzhiyun #define SMC_CMD_CPU0AFTR (-5) 17*4882a593Smuzhiyun #define SMC_CMD_SAVE (-6) 18*4882a593Smuzhiyun #define SMC_CMD_SHUTDOWN (-7) 19*4882a593Smuzhiyun /* For CP15 Access */ 20*4882a593Smuzhiyun #define SMC_CMD_C15RESUME (-11) 21*4882a593Smuzhiyun /* For L2 Cache Access */ 22*4882a593Smuzhiyun #define SMC_CMD_L2X0CTRL (-21) 23*4882a593Smuzhiyun #define SMC_CMD_L2X0SETUP1 (-22) 24*4882a593Smuzhiyun #define SMC_CMD_L2X0SETUP2 (-23) 25*4882a593Smuzhiyun #define SMC_CMD_L2X0INVALL (-24) 26*4882a593Smuzhiyun #define SMC_CMD_L2X0DEBUG (-25) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* For Accessing CP15/SFR (General) */ 29*4882a593Smuzhiyun #define SMC_CMD_REG (-101) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* defines for SMC_CMD_REG */ 32*4882a593Smuzhiyun #define SMC_REG_CLASS_SFR_W (0x1 << 30) 33*4882a593Smuzhiyun #define SMC_REG_ID_SFR_W(addr) (SMC_REG_CLASS_SFR_W | ((addr) >> 2)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ 42*4882a593Smuzhiyun #define OP_TYPE_CORE 0x0 43*4882a593Smuzhiyun #define OP_TYPE_CLUSTER 0x1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ 46*4882a593Smuzhiyun #define SMC_POWERSTATE_IDLE 0x1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif 49