1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Cloned from linux/arch/arm/mach-realview/headsmp.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2003 ARM Limited 6*4882a593Smuzhiyun * All Rights Reserved 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun#include <linux/linkage.h> 9*4882a593Smuzhiyun#include <linux/init.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include <asm/assembler.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/* 14*4882a593Smuzhiyun * exynos4 specific entry point for secondary CPUs. This provides 15*4882a593Smuzhiyun * a "holding pen" into which all secondary cores are held until we're 16*4882a593Smuzhiyun * ready for them to initialise. 17*4882a593Smuzhiyun */ 18*4882a593SmuzhiyunENTRY(exynos4_secondary_startup) 19*4882a593SmuzhiyunARM_BE8(setend be) 20*4882a593Smuzhiyun mrc p15, 0, r0, c0, c0, 5 21*4882a593Smuzhiyun and r0, r0, #15 22*4882a593Smuzhiyun adr r4, 1f 23*4882a593Smuzhiyun ldmia r4, {r5, r6} 24*4882a593Smuzhiyun sub r4, r4, r5 25*4882a593Smuzhiyun add r6, r6, r4 26*4882a593Smuzhiyunpen: ldr r7, [r6] 27*4882a593Smuzhiyun cmp r7, r0 28*4882a593Smuzhiyun bne pen 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * we've been released from the holding pen: secondary_stack 32*4882a593Smuzhiyun * should now contain the SVC stack for this core 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun b secondary_startup 35*4882a593SmuzhiyunENDPROC(exynos4_secondary_startup) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun .align 2 38*4882a593Smuzhiyun1: .long . 39*4882a593Smuzhiyun .long exynos_pen_release 40